max9744 Maxim Integrated Products, Inc., max9744 Datasheet - Page 18

• Manufacturer Part Number: max9744
• Description: 20w Stereo Class D Speaker Amplifier With Volume Control
• Manufacturer: Maxim Integrated Products, Inc.

20W Stereo Class D Speaker Amplifier
with Volume Control
A write to the MAX9744 includes transmission of a
START condition, the slave address with the R/W bit set
to 0 (see Table 3), one byte of data to the command
register, and a STOP condition. Figure 6 illustrates the
proper format for one frame.
A write to the MAX9744 consists of a 6-step sequence
as seen below:
The command register is used to control the volume
level of the speaker amplifier. The two MSBs (A1 and
A0) are set to 00, while V5–V0 is the data that is written
into the addresses register to set the volume level
(Tables 5 and 6).
Table 5. Data Byte Format
Table 6. Command Register Programming
18
1) The master sends a START condition.
2) The master sends the 7 bits slave ID plus a write
3) The addressed slave asserts an ACK on the data
4) The master sends 8 data bits.
5) The active slave asserts an ACK (or NACK) on the
6) The master generates a stop condition.
D7 (MSB)
A
______________________________________________________________________________________
bit (low).
line.
data line.
00
01
01
0
A1
A
1
XXXXXX
000000
000001
V5–V0
D6
A0
Speaker Volume Control
Volume level (Table 7)
Filterless modulation
Classic PWM
D5
V5
SETTING
Write Byte
D4
V4
The MAX9744 features two output modulation schemes:
filterless modulation or classic PWM, selectable through
the I
to set the output scheme.
When switching between schemes, the output is not
click-and-pop protected. To have click-and-pop protec-
tion when switching between output schemes, the
device must enter shutdown mode and be configured
to the new output scheme before the 220ms startup
sequence is terminated.
Figure 6. Write Byte Format Example
WRITE BYTE FORMAT
S
D3
V3
A
2
C interface. Table 6 shows the register command
10
11
11
0
A
1
SLAVE
SLAVE ADDRESS:
EQUIVALENT TO CHIP-
SELECT LINE OF A
3-WIRE INTERFACE.
7 BITS
ADDRESS
D2
V2
XXXXXX
000100
000101
V5–V0
WR
0
Filterless Modulation/PWM
ACK
D1
V1
Reserved
Increased volume
Decreased volume
DATA BYTE: GIVES A COMMAND.
8 BITS
DATA
SETTING
D0 (LSB)
ACK
V0
P