max9234eumtd Maxim Integrated Products, Inc., max9234eumtd Datasheet
max9234eumtd
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Rev 0; 4/05 Hot-Swappable, 21-Bit, DC-Balanced LVDS General Description The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers ABSOLUTE MAXIMUM RATINGS V to GND ...........................................................-0.5V to +4. GND.........................................................-0.5V to +6.0V CCO RxIN_, RxCLK IN_ to GND ....................................-0.5V to +4.0V PWRDWN to GND....................................................-0.5V to 6.0V RxOUT_, RxCLK OUT to GND ................-0.5V ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS DC ELECTRICAL CHARACTERISTICS (continued) = +3.0V to +5.5V, PWRDWN = high, differential input voltage +3.0V to +3.6V CCO = V /2 to 2.4V - V mode voltage +3.3V, ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers AC ELECTRICAL CHARACTERISTICS ( +3.0V to +3.6V, 100mV CC CCO 0.1V to 1.2V, input common mode voltage V = +3.3V, V values are CCO ID PARAMETER SYMBOL ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS = 8pF, PWRDWN = high, differential input voltage +3.3V CCO +25°C, unless otherwise noted.) A MAX9234/MAX9236 WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCY 100 90 ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers PIN NAME 45, RxOUT14–RxOUT20 Channel 2 Single-Ended Outputs 46 25, 32, 38, GND Ground 44 6 N.C. No Connect 7, 13, 18 LVDS GND LVDS Ground 8 RxIN0- Inverting ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS Table 1. Part Equivalent Table PART EQUIVALENT WITH DCB/NC = HIGH OR OPEN MAX9234 MAX9236 MAX9238 Detailed Description The MAX9234/MAX9236 operate at a parallel clock fre- quency of 8MHz to 34MHz. The MAX9238 operates at a ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers RxOUT_ OR RxCLK OUT 8pF Figure 3. Output Load and Transition Times IDEAL SERIAL BIT TIME RSKM RSKM IDEAL MIN MAX INTERNAL STROBE Figure 4. LVDS Receiver Input Skew Margin RCIP RxCLK OUT 2.0V 2.0V ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS PWRDWN 0.8V RxCLK IN RxOUT_ RxCLK OUT Figure 8. Power-Down Delay MAX9234/MAX9236/MAX9238 vs. MAX9210/MAX9220/MAX9222 The MAX9234/MAX9236/MAX9238 operate in DC-bal- ance mode only. Pinouts are the same as the MAX9210/MAX9220/MAX9222 except that pin 6 on the MAX9234/MAX9236/MAX9238 ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers MAX9209 MAX9211 MAX9213 MAX9215 2):1 7 TxIN (7 + 2): 2):1 PWRDWN PLL TxCLK IN 21:3 SERIALIZER Figure 10. Two Capacitors per Link, AC-Coupled MAX9209 MAX9211 MAX9213 MAX9215 7 ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS In the following example, the capacitor value for a droop calculated. Jitter due to this droop is then calculated assuming a 1ns transition time DSV) / ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers Power-Supply Bypassing There are separate on-chip power domains for digital circuits, outputs, PLL, and LVDS inputs. Bypass each PLL V , and LVDS V CC CCO CC CC quency, surface-mount ceramic ...
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Hot-Swappable, 21-Bit, DC-Balanced LVDS In the following example, the incremental supply current is calculated for V = 5.5V 34MHz, and C CCO 5.5V - 3. 6pF ...
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... H BOTTOM VIEW SEE DETAIL SEATING PLANE END VIEW PARTING LINE L DETAIL A Printed USA is a registered trademark of Maxim Integrated Products, Inc. Package Information ; b b1 WITH PLATING c1 c BASE METAL SECTION C-C DALLAS SEMICONDUCTOR PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 48L TSSOP, 6.1mm BODY APPROVAL DOCUMENT CONTROL NO ...