max9234eumtd Maxim Integrated Products, Inc., max9234eumtd Datasheet - Page 12

• Manufacturer Part Number: max9234eumtd
• Description: Hot-swappable, 21-bit, Dc-balanced Lvds Deserializers
• Manufacturer: Maxim Integrated Products, Inc.

Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
V
quency, surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smallest value capacitor closest to the
supply pin.
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer PC
board with separate layers for power, ground, LVDS
inputs, and digital signals is recommended.
The MAX9234/MAX9236/MAX9238 ESD tolerance is
rated for Human Body Model and ISO 10605 standards.
ISO 10605 specifies ESD tolerance for electronic sys-
tems. The Human Body Model discharge components
are C
Human Body Model, all pins are rated for ±5kV contact
discharge. The ISO 10605 discharge components are
C
the LVDS outputs are rated for ±8kV contact and ±25kV
air discharge.
Figure 12. Human Body ESD Test Circuit
12
CC
S
= 330pF and R
, V
______________________________________________________________________________________
VOLTAGE
SOURCE
S
HIGH-
CCO
DC
= 100pF and R
, PLL V
CHARGE-CURRENT-
LIMIT RESISTOR
CC
1MΩ
D
R1
100pF
= 2kΩ (Figure 13). For ISO 10605,
, and LVDS V
C
S
Power-Supply Bypassing
D
Cables and Connectors
= 1.5kΩ (Figure 12). For the
RESISTANCE
DISCHARGE
STORAGE
CAPACITOR
1.5kΩ
R2
CC
ESD Protection
Board Layout
pin with high-fre-
DEVICE
UNDER
TEST
PWRDWN is 5V tolerant and is internally pulled down to
GND.
Skew margin (RSKM) is the time allowed for degrada-
tion of the serial data sampling setup and hold times by
sources other than the deserializer. The deserializer
sampling uncertainty is accounted for and does not
need to be subtracted from RSKM. The main outside
contributors of jitter and skew that subtract from RSKM
are interconnect intersymbol interference, serializer
pulse position uncertainty, and pair-to-pair path skew.
The outputs have a separate supply (V
to systems with 1.8V to 5V nominal input-logic levels. The
DC Electrical Characteristics table gives the maximum
supply current for V
switching frequencies with all outputs switching in the
worst-case switching pattern. The approximate incremen-
tal supply current for V
8pF load and worst-case pattern can be calculated using:
where:
I
C
tance.
V
f
The incremental current is added to (for V
or subtracted from (for V
Characteristics table maximum supply current. The
internal output buffer capacitance is C
worst-case pattern-switching frequency of the data out-
puts is half the switching frequency of the output clock.
V
Figure 13. ISO 10605 Contact Discharge ESD Test Circuit
I
C
I
T
= incremental supply current.
CCO
= incremental supply voltage.
= output clock-switching frequency.
= total internal (C
VOLTAGE
SOURCE
HIGH-
Output Supply and Power Dissipation
DC
I
I
= C
CHARGE-CURRENT-
LIMIT RESISTOR
+ C
T
50Ω TO 100Ω
V
T
I
V
CCO
0.5f
R1
330pF
INT
I
f
C
CCO
C
S
) and external (C
C
x 1 (clock output)
= 3.6V with 8pF load at several
CCO
x 21 (data outputs)
other than 3.6V with the same
RESISTANCE
DISCHARGE
STORAGE
CAPACITOR
Skew Margin (RSKM)
2kΩ
< 3.6V) the DC Electrical
R2
5V Tolerant Input
CCO
INT
L
) for interfacing
) load capaci-
CCO
= 6pF. The
DEVICE
UNDER
TEST
> 3.6V)