max9322ecytd Maxim Integrated Products, Inc., max9322ecytd Datasheet - Page 10

• Manufacturer Part Number: max9322ecytd
• Description: Max9322 Lvecl/lvpecl 1 15 Differential Divide-by-1/divide-by-2 Clock Driver
• Manufacturer: Maxim Integrated Products, Inc.

The differential clock input can be configured to accept
a single-ended input when operating at V
3.0V to 3.8V. Connect V
ing input of the differential input as a reference for sin-
gle-ended operation. The differential CLK_ input is
converted to a noninverting, single-ended input by con-
necting V
input signal to CLK. Similarly, an inverting configuration
is obtained by connecting V
the single-ended input to CLK_.
The single-ended inputs FSEL_, CLK_SEL, and MR are
internally referenced to V
(FSEL_, CLK_SEL, MR, and any CLK_ in single-ended
mode) can be driven to V
ended LVPECL/LVECL signal. The single-ended input
must be at least V
V
Characteristics table. When using the V
output, bypass V
V
ence can source or sink 0.5mA. Use V
ence for the same device only.
LVECL/LVPECL 1:15 Differential
Divide-by-1/Divide-by-2 Clock Driver
Figure 4. Timing Diagram for MR Resynchronization
10
CC
OH
. Leave V
______________________________________________________________________________________
and V
BB
OL
Q_(÷1)
Q_(÷2)
to CLK_ and connecting the single-ended
CLK_
BB
MR
levels specified in the DC Electrical
BB
open when not used. The V
BB
Single-Ended Inputs and V
with a 0.01µF ceramic capacitor to
±95mV to switch the outputs to the
BB
CC
BB
to the inverting or noninvert-
BB
. All single-ended inputs
and V
to CLK_ and connecting
EE
or with a single-
BB
BB
CC
as a refer-
reference
BB
- V
refer-
EE
BB
=
Bypass each V
surface-mount ceramic 0.01µF and 0.1µF capacitors in
parallel as close to the device as possible, with the
0.01µF capacitor closest to the device. Use multiple
parallel vias to minimize parasitic inductance. When
using the V
with a 0.01µF ceramic capacitor.
Input and output trace characteristics affect the perfor-
mance of the MAX9322. Connect input and output sig-
nals with 50Ω characteristic impedance traces.
Minimize the number of vias to prevent impedance dis-
continuities. Reduce reflections by maintaining the 50Ω
characteristic impedance through cables and connec-
tors. Reduce skew within a differential pair by matching
the electrical length of the traces.
Terminate outputs with 50Ω to V
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if QA0 is used as a single-ended
output, terminate both QA0 and QA0.
BB
CC
Applications Information
reference output, bypass V
Controlled-Impedance Traces
and V
CCO
to V
Output Termination
Supply Bypassing
EE
CC
with high-frequency
- 2V or use an
BB
to V
CC