max9322ecytd Maxim Integrated Products, Inc., max9322ecytd Datasheet - Page 6

• Manufacturer Part Number: max9322ecytd
• Description: Max9322 Lvecl/lvpecl 1 15 Differential Divide-by-1/divide-by-2 Clock Driver
• Manufacturer: Maxim Integrated Products, Inc.

LVECL/LVPECL 1:15 Differential
Divide-by-1/Divide-by-2 Clock Driver
6
14, 27, 30,
39, 40, 47,
_______________________________________________________________________________________
TQFP
10
11
12
13
52
15
16
17
18
1
2
3
4
5
6
7
8
9
PIN
54, 61, 66, 67
19, 20, 33,
36, 37, 40,
49, 50, 53,
15, 16
QFN
2, 3
10
11
12
13
14
21
22
23
24
4
5
6
7
8
9
CLK_SEL
FSELA
FSELB
FSELC
FSELD
NAME
CLK0
CLK1
V
CLK0
CLK1
V BB
QD5
QD5
QD4
QD4
V
V
MR
CCO
CC
EE
Positive Power Supply. Powers input circuitry. Bypass each V
and 0.1µF capacitor. Place the capacitors as close to the device as possible with the
smaller value capacitor closest to the device.
Single-Ended Master Reset. A high on MR sets all outputs to differential zero. A low on
MR enables all outputs. MR is pulled to V
Single-Ended Frequency Select A. Selects the output frequency for bank A. Bank A
consists of two differential outputs. A low on FSELA selects divide-by-1. A high on
FSELA selects divide-by-2. FSELA is pulled to V
Single-Ended Frequency Select B. Selects the output frequency for bank B. Bank B
consists of three differential outputs. A low on FSELB selects divide-by-1. A high on
FSELB selects divide-by-2. FSELB is pulled to V EE through a 75kΩ resistor.
Noninverting Clock 0 Input. CLK0 is pulled to V EE through 75kΩ resistors.
Inverting Clock 0 Input. CLK0 is pulled to V
Single-Ended Clock Selector Input. A low on CLK_SEL selects CLK0. A high on
CLK_SEL selects CLK1. CLK_SEL is pulled to V
Noninverting Clock 1 Input. CLK1 is pulled to V
Inverting Clock 1 Input. CLK1 is pulled to V
Reference Voltage Output. Connect V
single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to V
otherwise leave open.
Single-Ended Frequency Select C. Selects the output frequency for bank C. Bank C
consists of four differential outputs. A low on FSELC selects divide-by-1. A high on
FSELC selects divide-by-2. FSELC is pulled to V EE through a 75kΩ resistor.
Single-Ended Frequency Select D. Selects the output frequency for bank D. Bank D
consists of six differential outputs. A low on FSELD selects divide-by-1. A high on
FSELD selects divide-by-2. FSELD is pulled to V
Negative Power-Supply Input
Output Driver Positive Power Supply. Powers device output drivers. Bypass each V
to V
as possible with the smaller value capacitor closest to the device.
Inverting QD5 Output. Typically terminate with 50Ω resistor to V
Noninverting QD5 Output. Typically terminate with 50Ω resistor to V
Inverting QD4 Output. Typically terminate with 50Ω resistor to V
Noninverting QD4 Output. Typically terminate with 50Ω resistor to V
EE
with a 0.01µF and 0.1µF capacitor. Place the capacitors as close to the device
BB
FUNCTION
to CLK_ or CLK_ to provide a reference for
EE
CC
CC
through a 75kΩ resistor.
and to V
and to V
EE
EE
EE
EE
through a 75kΩ resistor.
through a 75kΩ resistor.
through a 75kΩ resistor.
through a 75kΩ resistor.
EE
EE
through a 75kΩ resistor.
through 75kΩ resistors.
Pin Description
CC
CC
CC
to V
- 2V.
- 2V.
CC
CC
EE
- 2V.
- 2V.
with a 0.01µF
CC
CCO
;