pck9447 NXP Semiconductors, pck9447 Datasheet - Page 7

• Manufacturer Part Number: pck9447
• Description: 3.3 V/2.5 V 1 9 Lvcmos Clock Fan-out Buffer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 9:
T
[1]
[2]
[3]
[4]
9397 750 12522
Product data sheet
Symbol
f
f
t
t
t
t
t
t
t
t
t
t
i
o
W(i)(ref)
PLH
PLZ
PZL
su
h
sk(o)
sk(pr)
sk(p)
r
amb
Fig 3. Output clock stop (CLK_STOP) timing diagram
Fig 4. Cycle-to-cycle jitter time
o
, t
f
, t
, t
, t
CLK_STOP
Dynamic characteristics apply for parallel output termination of 50
Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference
input pulse width, output duty cycle, and maximum frequency specifications. CCLK0, CCLK1; 0.7 V to 1.7 V.
Setup and hold times are referenced to the falling edge of the selected clock signal input.
Pulse skew time is the absolute difference of the propagation delay times: t
= 40 C to +85 C; V
PHZ
PZH
PHL
Q0 to Q8
CCLK0
CCLK1
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs.
or
Dynamic characteristics (2.5 V)
Parameter
input frequency
output frequency
reference input pulse width
propagation delay
output disable time
output enable time
setup time
hold time
output skew time
process skew time
pulse skew time (output)
output duty cycle
output rise/fall time
CC
= 2.5 V
5 %
t
N
t
[1] [2]
jit(cc)
Conditions
CCLK0 or CCLK1 to any Q
CCLK0 or CCLK1 to CLK_STOP
CCLK0 or CCLK1 to CLK_STOP
output-to-output
part-to-part
f
0.6 V to 1.8 V
q
< 170 MHz;
= t
Rev. 01 — 13 October 2005
N
t
N+1
t
N+1
ref
= 50 %
to V
TT
.
3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer
PLH
– t
PHL
.
[3]
[3]
[4]
Min
0
0
1.4
1.7
-
-
0.0
1.0
-
-
-
45
0.1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
002aab293
Typ
-
-
-
-
-
-
-
-
-
-
-
50
-
PCK9447
Max
350
350
-
4.4
11
11
-
-
150
2.7
200
55
1.0
002aaa717
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ps
ns
ps
%
ns
7 of 17