adf4108bruz-rl Analog Devices, Inc., adf4108bruz-rl Datasheet

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adf4108bruz-rl

Manufacturer Part Number
adf4108bruz-rl
Description
Pll Frequency Synthesizer
Manufacturer
Analog Devices, Inc.
Datasheet
FEATURES
8.0 GHz bandwidth
3.2 V to 3.6 V power supply
Separate charge pump supply (V
Programmable, dual modulus prescaler 8/9, 16/17, 32/33, or
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
Loop filter design possible with ADIsimPLL
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
voltage in 3.3 V systems
64/65
RF
RF
REF
DATA
CLK
IN
IN
LE
IN
A
B
24-BIT INPUT
REGISTER
SD
OUT
PRESCALER
FUNCTION
AV
CE
LATCH
P/P + 1
FROM
DD
22
P
N = BP + A
AGND DGND
DV
) allows extended tuning
DD
A, B COUNTER
R COUNTER
R COUNTER
FUNCTION
LATCH
LATCH
LATCH
14-BIT
LOAD
LOAD
B COUNTER
A COUNTER
FUNCTIONAL BLOCK DIAGRAM
14
13-BIT
6-BIT
6
13
19
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The ADF4108 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise digital PFD (phase frequency detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual-modulus prescaler (P/P + 1). The
A (6-bit) and B (13-bit) counters, in conjunction with the dual-
modulus prescaler (P/P + 1), implement an N divider (N =
BP + A). In addition, the 14-bit reference counter (R counter),
allows selectable REFIN frequencies at the PFD input. A
complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
V
P
FREQUENCY
DETECTOR
DETECT
PLL Frequency Synthesizer
CPGND
PHASE
LOCK
SD
AV
OUT
DD
CPI3 CPI2 CPI1
SETTING 1
CURRENT
M3 M2 M1
©2006 Analog Devices, Inc. All rights reserved.
MUX
REFERENCE
CHARGE
PUMP
ADF4108
CPI6 CPI5 CPI4
HIGH Z
SETTING 2
CURRENT
R
SET
ADF4108
CP
MUXOUT
www.analog.com

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adf4108bruz-rl Summary of contents

Page 1

... One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ADF4108 R SET REFERENCE CHARGE CP PUMP CURRENT CURRENT SETTING 1 SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 HIGH MUXOUT MUX SD OUT ADF4108 www.analog.com ©2006 Analog Devices, Inc. All rights reserved. ...

Page 2

ADF4108 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Rating ............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. ...

Page 3

SPECIFICATIONS 3.3 V ± 2%, AV ≤ unless otherwise noted. MAX Table 1. Parameter B Version RF CHARACTERISTICS RF Input Frequency (RF ) 1.0/8 Input Sensitivity −5/+5 ...

Page 4

ADF4108 Parameter B Version NOISE CHARACTERISTICS 9 Normalized Phase Noise Floor −219 10 Phase Noise Performance 11 7900 MHz Output −81 Spurious Signals 7900 MHz Output 11 –61 1 Operating temperature range (B version) is –40°C to +85°C. 2 The ...

Page 5

TIMING CHARACTERISTICS 3.3 V ± 2%, AV ≤ unless otherwise noted. MAX Table 2. 1 Parameter Limit ...

Page 6

ADF4108 ABSOLUTE MAXIMUM RATING T = 25°C, unless otherwise noted. A Table 3. Parameter GND GND Digital I/O Voltage to GND Analog I/O ...

Page 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SET CPGND ADF4108 TOP VIEW 4 13 AGND (Not to Scale REF 9 ...

Page 8

ADF4108 TYPICAL PERFORMANCE CHARACTERISTICS FREQ UNIT: GHz KEYWORD: R PARAM TYPE: s DATA FORMAT: MA Freq MAGS11 ANGS11 Freq 4.30000 0.50000 0.89148 –17.2820 0.88133 –20.6919 4.40000 0.60000 0.70000 0.87152 –24.5386 4.50000 0.80000 0.85855 –27.3228 4.60000 4.70000 0.90000 0.84911 –31.0698 0.83512 ...

Page 9

THEORY OF OPERATION REFERENCE INPUT STAGE The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ...

Page 10

ADF4108 DIVIDER CLR1 PROGRAMMABLE U3 DELAY ABP2 ABP1 CLR2 DOWN DIVIDER Figure 14. PFD Simplified Schematic and Timing (in Lock) MUXOUT AND LOCK DETECT The output multiplexer on the ...

Page 11

LATCH SUMMARY ANTI- TEST BACKLASH RESERVED MODE BITS WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 LDP T2 T1 ABP2 RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 ...

Page 12

ADF4108 REFERENCE COUNTER LATCH MAP TEST BACKLASH RESERVED MODE BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 0 0 LDP T2 T1 ABP2 DON’T CARE ABP2 ...

Page 13

AB COUNTER LATCH MAP RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 B13 B12 B11 B10 X = DON’T CARE B13 B12 B11 ...

Page 14

ADF4108 FUNCTION LATCH MAP CURRENT CURRENT PRESCALER SETTING SETTING VALUE 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 TC4 ...

Page 15

INITIALIZATION LATCH MAP CURRENT CURRENT PRESCALER SETTING SETTING VALUE 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 TC4 ...

Page 16

ADF4108 FUNCTION LATCH The on-chip function latch is programmed with C2 and C1 set to 1 and 0, respectively. Figure 19 shows the input data format for programming the function latch. Counter Reset DB2 (F1) is the counter reset bit. ...

Page 17

Charge Pump Currents CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Figure 19. Prescaler Value P2 and P1 ...

Page 18

ADF4108 INTERFACING The ADF4108 has a simple SPI™-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE (Latch Enable) goes high, the 24 bits that have been clocked into the input register ...

Page 19

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-20) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the ...

Page 20

... SEATING PLANE ORDERING GUIDE Model Temperature Range 1 ADF4108BRUZ −40°C to +85°C 1 ADF4108BRUZ-RL −40°C to +85°C 1 ADF4108BRUZ-RL7 −40°C to +85°C ADF4108BCPZ 1 −40°C to +85°C 1 ADF4108BCPZ–RL −40°C to +85°C 1 ADF4108BCPZ–RL7 −40°C to +85°C EVAL-ADF4108EB1 Pb-free part. ...

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