adf4108bruz-rl Analog Devices, Inc., adf4108bruz-rl Datasheet - Page 7

• Manufacturer Part Number: adf4108bruz-rl
• Description: Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin No.
LFCSP_VQ
19
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
Figure 3. TSSOP Pin Configuration for TSSOP
NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
CPGND
AGND
RF
RF
REF
AV
R
SET
IN
IN
CP
DD
IN
B
A
Mnemonic
R
CP
CPGND
AGND
RF
RF
AV
REF
DGND
CE
CLK
DATA
LE
MUXOUT
DV
V
1
2
3
4
5
6
7
8
SET
P
IN
IN
DD
(Not to Scale)
DD
ADF4108
IN
B
A
TOP VIEW
16
15
14
13
12
11
10
9
Description
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the R
with R
Charge Pump Output. When enabled, this pin provides ±I
drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF. See Figure 12.
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This voltage may range from 3.2 V to 3.6 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AV
as DV
Reference Input. This is a CMOS input with a nominal threshold of V
resistance of 100 kΩ. See Figure 11. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high will power up the device, depending on the status of the
power-down bit, F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
Serial Data Input. The serial data is loaded MSB first with the 2 LSBs being the control bits. This input
is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches, the latch being selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Power Supply. This may range from 3.2 V to 3.6 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
Charge Pump Power Supply. This voltage should be greater than or equal to V
V
V
DV
MUXOUT
LE
DATA
CLK
CE
DGND
DD
P
I
DD
is 3.3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
CP
DD
SET
MAX
.
= 5.1 kΩ, I
=
R
25
SET
5 .
CP MAX
Rev. 0 | Page 7 of 20
= 5 mA.
SET
pin is 0.66 V. The relationship between I
CPGND 1
AGND 2
AGND 3
RF
RF
Figure 4. LFCSP_VQ Pin Configuration
IN
IN
B 4
A 5
CP
DD
(Not to Scale)
ADF4108
to the external loop filter, which in turn
TOP VIEW
must be the same value as AV
PIN 1
INDICATOR
DD
/2 and a dc equivalent input
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
DD
must be the same value
DD
. In systems where
CP
and R
ADF4108
SET
DD
is
.