adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 12

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

ADF4196
PFD AND CHARGE PUMP
The PFD takes inputs from the R divider and N divider and
produces up and down outputs with a pulse width difference
that is proportional to the phase difference between the inputs.
The charge pump outputs a net up or down current pulse of
a width that is equal to this difference, to pump up or pump down
the voltage that is integrated into the loop filter, which in turn
increases or decreases the VCO output frequency. If the N divider
phase lags the R divider phase, a net up-current pulse is produced
that increases the VCO frequency (and, thus, the phase). If the
N divider phase leads the R divider edge, a net down-current
pulse is produced to reduce the VCO frequency and phase.
Figure 23 is a simplified schematic of the PFD and charge pump.
The charge pump is made up of an array of 64 identical cells,
each of which is fully differential. All 64 cells are active during
fast lock, and only one cell is active during normal operation.
Because a single-ended control voltage is required to tune the VCO,
an on-chip differential-to-single-ended amplifier is provided for
this purpose. In addition, because the phase-locked loop controls
only the differential voltage generated across the charge pump
outputs, an internal common-mode feedback (CMFB) loop
biases the charge pump outputs at a common-mode voltage of
approximately 2 V.
DIFFERENTIAL CHARGE PUMP
The charge pump cell has a fully differential design for best up-
to-down current matching (see Figure 24). Good matching is
essential to minimize the phase offset created when switching
the charge pump current from its high value (in fast lock mode)
to its nominal value (in normal mode).
To pump up, the up switches are on, and the PMOS current sources
out through CP
loop filter capacitors that are connected to CP
NMOS current sink on CP
external loop filter capacitors that are connected to CP
Therefore, the differential voltage between CP
increases.
To pump down, PMOS current sources out through CP
NMOS current sinks in through CP
(CP
OUT+
Figure 23. PFD and Differential Charge Pump Simplified Schematic
, CP
R DIVIDER
N DIVIDER
OUT−
) differential voltage. The charge pump up/down
OUT+
D
D
, which increases the voltage on the external
CLR
CLR
Q
Q
OUT−
decreases the voltage on the
EN[64:1]
CHARGE
ARRAY
PUMP
[64:1]
OUT+
, which decreases the
CMFB
OUT+
OUT+
. Similarly, the
and CP
CP
CP
OUT+
OUT–
OUT−
OUT−
OUT−
.
and
Rev. B | Page 12 of 28
matching is improved by an order of magnitude over the
conventional single-ended charge pump that depends on the
matching of two different device types. The up/down matching
in this structure depends on how a PMOS matches a PMOS,
and how an NMOS matches an NMOS.
FAST LOCK TIMEOUT COUNTERS
Timeout counters, clocked at one-quarter of the PFD reference
frequency, are provided to precisely control the fast locking
operation (see Figure 25). When a new frequency is programmed,
the fast lock timers start and the PLL locks into wide bandwidth
mode with the 64 identical 100 µA charge pump cells active (for a
total of 6.4 mA).
When the I
reduced to 1× by deselecting cells in binary steps over the next
six timer clock cycles, until only one 100 µA cell is active. The
switching of the charge pump current, from 6.4 mA to 100 µA,
equates to an 8-to-1 change in loop bandwidth; when this happens,
the loop filter must be changed to ensure stability. The SW1,
SW2, and SW3 switches change the loop filter.
The applications circuit shown in Figure 37 shows how the
switches can be used to reconfigure the loop filter time constants.
They close to short out external loop filter resistors during fast lock
and open when their counters time out to restore the filter time
constants to their normal values for the 100 µA charge pump
current. Because it takes six timer clock cycles to reduce the
charge pump current to 1×, it is recommended that both switch
timers be pro-grammed to the value of the I
f
PFD
WRITE
TO R0
CP
÷4
START
counter times out, the charge pump current is
DOWN
Figure 24. Differential Charge Pump Cell
Figure 25. Fast Lock Timeout Counters
with External Loop Filter Components
UP
CHARGE PUMP
ENABLE LOGIC
COUNTER
TIMEOUT
EN[64:1]
P
N
I
CP
CP
OUT+
V
V
BIAS
BIAS
COUNTER
SW1/SW2
TIMEOUT
P
N
C
POUT–
N
P
CP
DOWN
UP
COUNTER
timer plus 7.
TIMEOUT
Data Sheet
SW3
SW3
A
SW1
SW2
SW
OUT
GND