el4584 Intersil Corporation, el4584 Datasheet

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el4584

Manufacturer Part Number
el4584
Description
Horizontal Genlock, 4fsc
Manufacturer
Intersil Corporation
Datasheet

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Horizontal Genlock, 4F
The EL4584 is a PLL (Phase Lock Loop) sub system,
designed for video applications but also suitable for general
purpose use up to 36MHz. In video applications, this device
generates a TTL/CMOS compatible Pixel Clock (CLK OUT)
which is a multiple of the TV horizontal scan rate and phase
locked to it.
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog
composite video signal with the EL4583 Sync Separator. An
input signal to “coast” is provided for applications were
periodic disturbances are present in the reference video
timing such as VTR head switching. The Lock detector
output indicates correct lock.
The divider ratio is four ratios for NTSC and four similar
ratios for the PAL video timing standards, by external
selection of three control pins. These four ratios have been
selected for common video applications including 4F
3F
elements used in some workstation graphics. To generate
8F
EL4585, which includes an additional divide-by-two stage.
For applications where these frequencies are inappropriate
or for general purpose PLL applications the internal divider
can be bypassed and an external divider chain used.
NOTES:
Divisor
PAL F
Divisor
NTSC F
1. 3F
2. CCIR 601 Divisors yield 720 pixels in the portion of each line for
3. Square pixels format gives 640 pixels for NTSC and 768 pixels
SC
SC
FUNCTION
NTSC and PAL.
for PAL in the active portion.
, 13.5MHz (CCIR 601 format) and square picture
, 6F
SC
OSC
OSC
numbers do not yield integer divisors.
SC
(MHz)
, 27MHz (CCIR 601 format) etc. use the
MHz)
FREQUENCIES AND DIVISORS
(NOTE 1)
13.301
10.738
3F
851
682
SC
®
CCIR 601
(NOTE 2)
1
13.5
13.5
864
858
SC
Data Sheet
SQUARE
(NOTE 3)
12.273
14.75
944
780
17.734
14.318
SC
4F
1135
910
1-888-INTERSIL or 1-888-468-3774
SC
,
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• 36MHz, general purpose PLL
• 4F
• Compatible with EL4583 sync separator
• VCXO, Xtal, or LC tank oscillator
• < 2ns jitter (VCXO)
• User controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed TV scan rate clock divisors
• Selectable external divide for custom ratios
• Single 5V, low current operation
• Pb-Free plus anneal available (RoHS compliant)
Applications
• Pixel clock regeneration
• Video compression engine (MPEG) clock generator
• Video capture or digitization
• PIP (Picture in Picture) timing generator
• Text or graphics overlay timing
Ordering Information
Demo Board
A demo PCB is available for this product.
EL4584CN
EL4584CS
EL4584CS-T7
EL4584CS-T13
EL4584CSZ
(See Note)
EL4584CSZ-T7
(See Note)
EL4584CSZ-T13
(See Note)
*For 6F
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
PART NUMBER
SC
SC
based timing (use the EL4585 for 8F
All other trademarks mentioned are the property of their respective owners.
and 8F
July 25, 2005
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
SC
Copyright Intersil Americas Inc.2003-2005. All Rights Reserved
16-Pin SO (0.150”)
16-Pin SO (0.150”)
16-Pin SO (0.150”)
16-Pin SO (0.150”)
16-Pin SO (0.150”)
16-Pin SO (0.150”)
clock frequencies, see EL4585 datasheet.
16-Pin PDIP
PACKAGE
(Pb-free)
(Pb-free)
(Pb-free)
TAPE &
REEL
13”
13”
7”
7”
-
-
-
EL4584
SC
FN7174.2
)
PKG. DWG.
MDP0027
MDP0027
MDP0027
MDP0031
MDP0027
MDP0027
MDP0027
#

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el4584 Summary of contents

Page 1

... Data Sheet Horizontal Genlock The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to it ...

Page 2

... Pinout EL4584 (16-PIN SO, PDIP) TOP VIEW 2 EL4584 FN7174.2 July 25, 2005 ...

Page 3

... OH = 3.2mA OL = -3.2mA OH = 200µ -200µ 2.5V OUT = 2.5V OUT = 2.5V OUT > V > OUT = 5V 25°C unless otherwise noted DD A CONDITIONS = 5V (Note 1) input to EL4584. Test for positive signal lock. SYNC CC MIN TYP MAX UNIT 1.5 V 3.5 V -100 nA 100 nA -100 -60 µA 60 100 µA 0 ...

Page 4

... EL4584 Digital inputs to select ÷ N value for internal counter. See table below for values. Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit. Analog positive supply for oscillator, PLL circuits. Input from external VCO. Analog ground for oscillator, PLL circuits. ...

Page 5

... Timing Diagrams FIGURE 1. PLL LOCKED CONDITION (PHASE ERROR = 0) 5 EL4584 θ Tθ = phase error period FIGURE 2. OUT OF LOCK CONDITION FIGURE 3. TEST CIRCUIT 1 Falling edge 110ns locks SYNC to rising edge of Ext Div signal. ) × 360° = (Tθ/ period ...

Page 6

... JA 0.8 0.6 SO16 (0.150”) θ 0.4 =110°C AMBIENT TEMPERATURE (°C) 6 EL4584 EL4584 OSC GAIN @ 20MHz vs TEMPERATURE OSC GAIN vs F OSC Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 2 1.8 1.6 1.43W 1.4 1.25W 1.2 1 0.8 0.6 0.4 0 ...

Page 7

... The clock is generated by the signal on pin 5, OSC in. There are 2 general types of VCO that can be used with the EL4584, LC and crystal controlled. Additionally, each type can be either built up using discrete components, including a varactor as the frequency controlling element, or complete, self contained modules can be purchased with everything inside a metal can ...

Page 8

... VCO frequency as constant a 8 EL4584 possible. VCO frequency will drift as charge leaks from the filter capacitor, and the voltage changes the VCO operating point. Coast mode is intended to be used when noise or signal degradation result in loss of horizontal sync for many cycles ...

Page 9

... NOTE: Use shielded inductors for optimum performance. FIGURE 5. TYPICAL XTAL VCO 9 EL4584 XTAL VCO COMPONENT VALUES (APPROXIMATE) FREQUENCY (MHz) 13.301 13.5 14.75 17.734 10.738 12.273 14.318 The above oscillators are arranged as Colpitts oscillators, and the structure is redrawn here to emphasize the split capacitance used in a Colpitts oscillator ...

Page 10

... Where ϖ = loop filter bandwidth, and ζ = loop filter damping n factor 300µA/2πrad = 4.77e-5A/rad for the EL4584 The loop bandwidth should be about H frequency/20, and the damping ratio should be 1 for optimum performance. For our example, ϖ = 15.734kHz/20 = 787Hz≈5000rad/S. ...

Page 11

... The entire oscillator/filter section should be surrounded by copper ground to prevent unwanted influences from nearby signals. Use separate paths for 11 EL4584 analog and digital supplies, keeping the analog (oscillator section) as short and free from spurious signals as possible. Careful attention must be paid to correct bypassing. Keep ...

Page 12

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 EL4584 (2) XTAL El Monte, CA 91731 (818) 443-2121 Varactors • ...

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