mc145167 Freescale Semiconductor, Inc, mc145167 Datasheet - Page 6

• Manufacturer Part Number: mc145167
• Description: Dual Plls 46/49 Cordless Telephones
• Manufacturer: Freescale Semiconductor, Inc

INPUT PINS
OSC in /OSC out
Reference Oscillator Input/Output (Pins 1,16)
an external parallel–resonant crystal. For a 46/49 MHz cord-
less phone application, a 10.24 MHz crystal is needed.
OSC in may also serve as input for an externally generated
reference signal. This signal is typically ac coupled to
OSC in , but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required for OSC out .
MODE
Mode Select (Pin 2)
the base or handset of a cordless phone. Internally, this pin is
used in the decoding logic for selecting the ROM address.
When high, the device is set in the base mode, and when
low, it is set in the handset mode. This input has an internal
pull–down device.
SB
Standby Input (Pin 3)
ting. When high, both the transmit and receive loops are in
operation. When low, the transmit loop is disabled, thereby
reducing power consumption. This input has an internal pull–
down device.
D0 – D3
Data Inputs (MC145166 — Pins 5 – 8)
of ten channels to be locked in both the transmit and receive
loop. When address data other than 1 – 10 are input, the de-
coding logic defaults to channel 10. The frequency assign-
ments with reference to Mode and D0 – D3 are shown in
Table 1. These inputs have internal pull–down devices.
f in1 , f in2
Frequency Inputs (Pins 14, 9)
transmit counters, respectively. These signals are typically
derived from the loop VCO and are ac coupled. For larger
amplitude signals (standard CMOS logic levels), dc coupling
may be used. The minimum input level is 200 mV p–p.
MC145166 MC145167
6
These pins form a reference oscillator when connected to
Mode is for determining whether the part is to be used in
The standby pin is used to save power when not transmit-
These inputs provide the BCD code for selecting the one
f in1 and f in2 are inputs to the divide–by–N receive and
PIN DESCRIPTIONS
CLK, DATA
Clock, Data (MC145167 — Pins 5, 6)
programming instead of parallel. Logical high represents a 1.
Each low–to–high transition of the clock shifts one bit of data
into the on–chip shift register.
ENB
Enable (MC145167 — Pin 8)
ister to the 4–bit latch. A positive pulse latches the data.
OUTPUT PINS
5 k
5 kHz Tone Signals (Pin 4)
puts derived from the reference oscillator.
LD
Lock Detect Signal (Pin 10)
The lock output goes high to indicate an out–of–lock condi-
tion. This is a P–channel open–drain output.
PD1, PD2
Phase Detector Outputs (Pins 13, 11)
phase detectors for use as loop error signals. Phase detector
gain is V DD /4
POWER SUPPLY
V SS
Negative Power Supply (Pin 12)
ground.
V DD
Positive Power Supply (Pin 15)
from + 2.5 to + 5.5 V with respect to V SS .
These pins provide the BCD input by using serial channel
The enable pin controls the data transfer from the shift reg-
The 5 kHz tone signals are N–channel, open–drain out-
The lock detect signal is associated with the transmit loop.
These are three–state outputs of the transmit and receive
Frequency f v > f r or f v leading: Output = Negative pulses
Frequency f v < f r or f v lagging: Output = Positive pulses
Frequency f v = f r and phase coincidence: Output = High–
This pin is the negative supply potential and is usually
This pin is the positive supply potential and may range
impedance state
volts per radian.
MOTOROLA