MC14013BDG ON Semiconductor, MC14013BDG Datasheet - Page 5

• Manufacturer Part Number: MC14013BDG
• Description: IC FLIP FLOP DUAL D 14-SOIC
• Manufacturer: ON Semiconductor
• Series: 4000Br
• Type: D-Typer

Specifications of MC14013BDG

• Function: Set(Preset) and Reset
• Output Type: Differential
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 14MHz
• Delay Time - Propagation: 50ns
• Trigger Type: Positive Edge
• Voltage - Supply: 3 V ~ 18 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Logic Family: 4000
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Invert/Non-Invert
• Operating Supply Voltage (typ): 3.3/5/9/12/15V
• Package Type: SOIC
• Propagation Delay Time: 450ns
• Low Level Output Current: 4.2mA
• High Level Output Current: -4.2mA
• Frequency (max): 7MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 18V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 14
• Circuit Type: Low-Power Schottky
• Current, Supply: 120 μA
• Function Type: D-Type
• Logic Function: Flip-Flop
• Logic Type: CMOS
• Number Of Circuits: Dual
• Temperature, Operating, Range: -55 to +125 °C
• Voltage, Supply: 3 to 18 VDC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Compliant
• Other names: MC14013BDG; MC14013BDGOS

Inputs R and S low.
20 ns
t
su
D
C
Q
(H)
t
PLH
Figure 1. Dynamic Signal Waveforms
t
WH
10%
(Data, Clock, and Output)
50%
90%
CLOCK
CLOCK
CLOCK
t
TLH
50%
10%
t
90%
D
su (L)
t
h
f
1
cl
T FLIP−FLOP
BINARY RIPPLE UP−COUNTER (Divide−by−2
D
C
D
C
D
C
MODIFIED RING COUNTER (Divide−by−(n+1))
50%
t
20 ns
90%
t
WL
THL
1
1
1
10%
Q
Q
Q
Q
Q
Q
t
PHL
n−STAGE SHIFT REGISTER
TYPICAL APPLICATIONS
20 ns
http://onsemi.com
V
V
V
V
V
V
DD
SS
DD
SS
OH
OL
D
C
D
C
C
D
5
2
2
2
Q
Q
Q
Q
Q
Q
SET OR
Q OR Q
CLOCK
RESET
20 ns
Figure 2. Dynamic Signal Waveforms
t
t
PLH
PHL
90%
(Set, Reset, Clock, and Output)
t
w
n
)
D
C
D
C
D
C
50%
n
n
n
20 ns
50%
th
th
th
Q
Q
Q
Q
Q
Q
90%
10%
20 ns
50%
t
t
w
Q
Q
Q
rem
10%
20 ns
V
V
V
V
V
V
DD
SS
DD
SS
OH
OL