clc030 National Semiconductor Corporation, clc030 Datasheet
clc030
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clc030 Summary of contents
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... The designer can thus customize the CLC030 to fit the desired application. At power-up or after a reset command, the CLC030 is auto- configured to a default operating condition. Separate power pins for the output driver, PLL and the serializer improve power supply rejection, output jitter and noise performance ...
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Typical Application www.national.com 2 20000301 ...
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Block Diagram 3 20000302 www.national.com ...
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... Connection Diagram www.national.com 64-Pin TQFP Order Number CLC030VEC See NS Package Number VEC-64A 4 20000303 ...
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Absolute Maximum Ratings is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the National Semicon- ductor Sales Office / Distributors for availability and specifi- cations. CMOS I/O ...
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DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter I (3.3V) Power Supply Current, DD 3.3V Supply, Total I (2.5V) Power Supply Current, DD 2.5V Supply, Total I (2.5V) Power Supply ...
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AC Electrical Characteristics Note 8: Average value measured between rising edges computed over at least one video field. Note 9: Intrinsic timing jitter is measured in accordance with SMPTE RP 184-1996, SMPTE RP 192-1996 and the applicable serial data transmission ...
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Test Circuit www.national.com 8 20000307 ...
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... ANCILLARY/CONTROL DATA PATH The 10-bit, bi-directional Ancillary and Control Data Port performs two distinct functions in the CLC030. First used to selectively load ancillary data into the Ancillary Data FIFO for insertion into the video data stream. The utilization ...
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... ACLK again. This second clock resets the port from drive to receive mode and readies the port for another access cycle. When control data is being read from the port, the CLC030 will output AD[9:8] as 10b (2XXh, where XX are output data AD[7:0]) and may be ignored by the monitoring system. ...
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... FIFO on the rising edge of ACLK. The user has the option of including a checksum in the ANC input data or of having the CLC030 calculate and append the checksum. The CLC030 will append the Ancillary Data Flag to each packet automatically before multiplexing with the video data ...
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... The VCO free-running frequency is inter- nally set. The parallel data clock V PLL. The PLL automatically generates the appropriate fre- 20000312 quency for the serial clock rate. Loop filtering is internal to the CLC030. The VCO has separate analog and digital power supply feeds: V pin 1, and V DPLLD 12 ...
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... The Pass/Fail bit in the TEST 0 control register indicates the test status errors have been detected, this bit will be set to logic-1 approximately 2 field intervals after TPG En- able is set. If errors have been detected in the internal circuitry of the CLC030, Pass/Fail will remain reset www.national.com ...
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... Bit 7 is the Pass/Fail indicator bit. CONFIGURATION AND CONTROL REGISTERS The configuration and control registers store data which configures the operational modes of the CLC030 or which result from its operation. Many of these registers can be mapped to the multi-function I/O bus to make them available as external I/O functions ...
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Device Operation (Continued) TABLE 1. Configuration and Control Data Register Summary Register Function Bits EDH Error (SD) 1 Full-Field Flags 5 Active Picture Flags 5 ANC Flags 5 EDH Force 1 EDH Enable 1 F/F Flag Error 1 A/P Flag ...
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Device Operation (Continued) TABLE 1. Configuration and Control Data Register Summary (Continued) Register Function Bits SAV 1 EAV 1 Lock Detect 1 VPG Filter Enable 1 Dither_Enable 1 Vert. Dither Enable 1 Scrambler_ Enable 1 NRZI_Enable 1 LSB_Clipping 1 SYNC_Detect_Enable ...
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Device Operation (Continued) TABLE 2. Control Register Bit Assignments (Continued) Bit 7 Bit 6 Bit 5 SWITCH POINT 3 (register address 1Ah) PROTECT(4) PROTECT(3) PROTECT(2) FORMAT 0 (register address 0Bh) reserved SD ONLY HD ONLY FORMAT 1 (register address 0Ch) ...
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... EDH information invalid. In the case of SMPTE 292M data, the CRC check characters are recalculated and inserted automatically regardless of the presence of CRC characters in the parallel data. After the CLC030 is reset, the initial state of the CRC check characters is 00h. www.national.com The EDH Enable bit enables operation of the EDH generator function ...
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... This bit can be used to delay automatic insertion of data into the serial data stream. The CLC030 can keep track ancillary packets in the FIFO. Incoming packet length versus available space in the FIFO is also tracked. The MSG TRACK bit in the control registers, when set, enables tracking of packets in the FIFO ...
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... Only reduces the time required for the CLC030 to establish frequency lock and determine the HD format being pro- cessed. The SD Only bit when set to a logic-1 locks the CLC030 into the standard definition data ranges and frequencies. In sys- tems designed to handle only standard definition signals, ...
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... PLL lock. If the system is not fully stable, the logic is automatically reset. LOCK DETECT also com- bines the function of indicating that the CLC030 has de- tected the video format being received. This format detect function involves determination of the major raster param- eters such as line length, number of video lines in a frame, and so forth ...
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Device Operation (Continued) Test Pattern Bit 5 Select Word > Bits 1=HD 1=Progressive 0=Interlaced Video Raster Standard 0=SD 1=PAL 0=NTSC 1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 260M) Ref. Black 1 PLL Path Path. 1 color ...
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Device Operation (Continued) TABLE 5. Test Pattern Selection Codes (Continued) Test Pattern Bit 5 Select Word > Bits 525 Line, 30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M) Ref. Black 0 PLL Path Path. 0 color Bars (SD ...
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Device Operation (Continued) TABLE 6. I/O Configuration Register Addresses for Control Register Functions Register Bit [5] [4] reserved Flag 0 0 Error AP Flag 0 0 Error ANC Flag 0 0 Error EDH Error 0 0 (SD) ...
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Device Operation (Continued) TABLE 6. I/O Configuration Register Addresses for Control Register Functions (Continued) Register Bit [5] [4] Chksum 1 0 Attach In reserved 1 0 VPG Filter 1 0 Enable Dither 1 0 Enable FIFO Insert 1 0 Enable ...
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Pin Descriptions Pin Name 1 V DDPLLD 2 V SSPLLD 3 IO0 4 IO1 5 DV0 6 DV1 7 DV2 8 DV3 9 DV4 10 V SSD 11 DV5 12 DV6 13 DV7 14 DV8 15 DV9 16 V DDD ...
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Pin Descriptions (Continued) Pin Name 50 ANC/CTRL 51 V DDSD 52 R PRE REF 53 R LVL REF 54 V SSSD 55 V SSSD 56 SDO 57 V DDLS 58 SDO 59 V SSLS 60 V DDZ 61 V SSPLLA ...
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... Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used recommended practice to use two vias at each power pin of the CLC030 as well as all RF bypass capacitor terminals. Dual vias reduce the intercon- nect inductance half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components ...
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... Deutsch Tel: +49 (0) 69 9508 6208 English www.national.com Français Tel: +33 ( 8790 64-Pin TQPF Order Number CLC030VEC NS Package Number VEC-64A 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness ...