74lv161db NXP Semiconductors, 74lv161db Datasheet - Page 9

• Manufacturer Part Number: 74lv161db
• Description: Presettable Synchronous 4-bit Binary Counter; Asynchronous Reset
• Manufacturer: NXP Semiconductors

1. Unless otherwise stated, all typical values are measured at T
2. Typical values are measured at V
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS (Continued)
NOTES:
AC WAVEFORMS
V
V
V
1997 May 15
SYMBOL
M
M
OL
Figure 1. Clock (CP) to outputs (Q
Presettable synchronous 4-bit binary counter;
asynchronous reset
= 1.5 V at V
= 0.5
the clock pulse width and the maximum clock frequency.
f
and V
max
the master reset to output (Q
t
t
MR INPUT
h
h
CP INPUT
CP INPUT
OUTPUT
and the master reset to clock (CP) removal times.
OUTPUT
Q
V
n
V
Q
OH
OH
, TC
OL
V
n
GND
GND
GND
V
, TC
V
CC
Figure 2. Master reset (MR) pulse width,
OH
OL
are the typical output voltage drop that occur with the output load.
V
V
V
I
Hold time
D PE CEP CET to
D
CP
Maximum clock
Maximum clock
pulse frequency
I
I
CC
at V
ulse frequency
n
, PE, CEP, CET to
PARAMETER
CC
2.7 V;
V
M
t
PHL
2.7 V;
V
M
t
W
t
PHL
t
1/f
W
V
M
max
n
CC
, TC) propagation delays
V
Figures 4 – 6
Figures 4 – 6
WAVEFORM
n
M
Figures 1, 6
, TC) propagation delays,
= 3.3 V.
t
rem
V
M
t
PLH
SV00576
SV00577
CONDITION
CONDITION
amb
3.0 to 3.6
3.0 to 3.6
V
CC
1.2
2.0
2.7
2.0
2.7
= 25 C
(V)
9
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 3. Input (CET) to output (TC) propagation delays.
TC OUTPUT
CP INPUT
PE INPUT
D
CET INPUT
n
INPUT
Figure 4. Set-up and hold times for input (D
V
V
GND
GND
GND
OL
OH
MIN
14
19
24
GND
V
V
V
0
0
0
I
I
I
V
I
–40 to +85 C
and parallel enable input (PE).
TYP
–35
–12
–7
V
–9
40
58
70
M
2
V
1
V
M
t
M
su
V
t
V
M
su
LIMITS
M
MAX
t
h
t
t
PLH
h
–40 to +125 C
MIN
12
16
20
0
0
0
Product specification
MAX
74LV161
t
su
t
su
t
t
h
PHL
t
n
h
)
UNIT
MHz
SV00579
SV00578
ns
ns