hsp45116a Intersil Corporation, hsp45116a Datasheet - Page 4

• Manufacturer Part Number: hsp45116a
• Description: Numerically Controlled Oscillator/modulator
• Manufacturer: Intersil Corporation

Pin Descriptions
MODPI/2PI
ENPHREG
ENOFREG
ENCFREG
ENTIREG
ENPHAC
CLROFR
MOD0-1
NAME
AD0-1
C0-15
LOAD
GND
V
CLK
WR
ENI
CS
CC
7, 20, 32, 48, 62, 73,
102, 111, 124, 132,
114, 119, 125, 131,
22, 34, 50, 87, 95,
83, 92, 98, 108,
54-61, 63-70
NUMBER
145, 159
143, 157
51, 52
35, 36
47
53
49
27
28
42
43
44
45
46
41
38
4
TYPE
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
+5V Power supply input.
Power supply ground input.
Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.
Address pins for selecting destination of C0-15 data. AD1 is the MSB.
Chip select (active low).
Write Enable. Data is clocked into the input register selected by AD0-1 on the rising edge of WR
when the CS line is low.
Clock. All registers, except the Control Registers clocked with WR, are clocked (when enabled)
by the rising edge of CLK.
Phase Register Enable (active low). Registered on chip by CLK. When active low, after being
clocked onto chip, ENPHREG enables the clocking of data into the Phase Register.
Frequency Offset Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENOFREG enables clocking of frequency offset data into the frequency
offset register.
Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENCFREG enables clocking of data into the Center Frequency Register.
Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENPHAC enables clocking of the Phase Accumulator Register.
Time Interval Control Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENTIREG enables clocking of data into the Time Accumulator Register.
Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by
CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and
imaginary input data register.
Modulo π/2π Select. When low, the Sine and Cosine ROMs are addressed modulo 2π (360
degrees). When high, the most significant address bit is held low so that the ROMs are addressed
modulo π (180 degrees). This input is registered on chip by clock. This control pin was included
for FFT processing.
Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active,
after being clocked onto chip, CLROFR zeros the data path from the Frequency Offset Register
to the frequency adder. New data can still be clocked into the Frequency Offset Register;
CLROFR does not affect the contents of the register.
Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback path
in the phase accumulator without clearing the Phase Accumulator Register.
External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90, 180,
or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of the phase
control path are set to zero.
These bits are loaded into the Phase Register when ENPHREG is low.
HSP45116A
MOD1
0
0
1
1
MOD0
0
1
0
1
DESCRIPTION
PHASE SHIFT (DEGREES)
270
180
90
0
May 7, 2007
FN4156.4