ad8383 Analog Devices, Inc., ad8383 Datasheet

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ad8383

Manufacturer Part Number
ad8383
Description
Low Cost 10-bit, 6-channel Output Decimating Lcd Decdriver
Manufacturer
Analog Devices, Inc.
Datasheet

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Part Number:
ad8383ACPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
FEATURES
High voltage drive to within 1.3 V of supply rails
Output short-circuit protection
High update rates
Fast, 100 Ms/s, 10-bit input data update rate
Low static power dissipation: 0.7 W
Voltage-controlled video reference (brightness) and
INV bit reverses polarity of video signal
3.3 V logic, 9 V to 18 V analog supplies
High accuracy voltage outputs
Laser trimming eliminates the need for adjustments
Flexible logic
STSQ/XFR allow parallel AD8383 operation at various
Fast settling into capacitive loads
Available in 48-lead 7 mm × 7 mm LFCSP package
APPLICATIONS
LCD analog column driver
PRODUCT DESCRIPTION
The AD8383 provides a fast, 10-bit latched decimating digital
input that drives six high voltage outputs. 10-bit input words are
sequentially loaded into six separate, high speed, bipolar DACs.
Flexible digital input format allows several AD8383s to be used
in parallel for higher resolution displays. STSQ synchronizes
sequential input loading, XFR controls synchronous output
updating, and R/L controls the direction of loading as either
left-to-right or right-to-left. Six channels of high voltage output
drivers drive to within 1.3 V of the rail. For maximum flexibility,
the output signal can be adjusted for dc reference, signal
inversion.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Includes STBY function
full-scale (contrast) output levels
resolutions
30 ns settling time to 0.25% into 150 pF load
Slew rate 460 V/µs
Low Cost 10-Bit, 6-Channel Output
The AD8383 is fabricated on the 26 V, fast bipolar XFHV
process developed by Analog Devices, Inc. This process
provides fast input logic, bipolar DACs with trimmed accuracy
and fast settling, high voltage, precision drive amplifiers on the
same chip.
The AD8383 dissipates 0.7 W nominal static power. The STBY
pin reduces power to a minimum with fast recovery.
The AD8383 is offered in a 48-lead, 7 mm × 7 mm × 0.85 mm
LFCSP package and operates over the commercial temperature
range of 0°C to 85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
DB(0:9)
STBY
STSQ
BYP
CLK
XFR
E/O
R/L
Decimating LCD DecDriver
VREFHI
AD8383
10
SEQUENCE
FUNCTIONAL BLOCK DIAGRAM
CONTROL
BIAS
VREFLO
10
© 2004 Analog Devices, Inc. All rights reserved.
10
10
10
10
10
10
CONTROL
2-STAGE
2-STAGE
2-STAGE
2-STAGE
2-STAGE
2-STAGE
SCALING
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
Figure 1
10
10
10
10
10
10
DAC
DAC
DAC
DAC
DAC
DAC
INV
V1
www.analog.com
AD8383
V2
VID0
VID1
VID2
VID3
VID4
VID5
®

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ad8383 Summary of contents

Page 1

... The AD8383 dissipates 0.7 W nominal static power. The STBY pin reduces power to a minimum with fast recovery. The AD8383 is offered in a 48-lead × × 0.85 mm LFCSP package and operates over the commercial temperature range of 0°C to 85°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...

Page 2

... AD8383 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Maximum Power Dissipation ..................................................... 5 Pin Configuration and Function Descriptions............................. 6 Timing Diagrams.............................................................................. 7 Theory of Operation ........................................................................ 8 Transfer Function and Analog Output Voltage ........................ 8 Applications....................................................................................... 9 External VBIAS Generation ........................................................ 9 REVISION HISTORY Revision 0: Initial Version PCB Design for Good Thermal Performance ........................ 10 Thermal Pad Design .................................................................. 10 Thermal Via Structure Design ...

Page 3

... T , DAC Code 450 to 800 MIN MAX VREFHI ≥ VREFLO VREFHI ≥ VREFLO To VREFLO Binary AVCC – VOH, VOL – AGND 50% of VIDx 50% of VIDx Theory of Operation section. Rev Page AD8383 Min Typ Max Unit –7.5 +7.5 mV –3.5 +3 AVCC – – ...

Page 4

... AD8383 SPECIFICATIONS (continued) Parameter VIDEO OUTPUT DYNAMIC PERFORMANCE Data Switching Slew Rate Invert Switching Slew Rate Data Switching Settling Time to 1% Data Switching Settling Time to 0.25% Invert Switching Settling Time to 1% Invert Switching Settling Time to 0.25% Invert Switching Overshoot CLK and Data Feedthrough ...

Page 5

... The AD8383 employs a 2-stage overload protection circuit that consists of an output current limiter and a thermal shutdown. 300°C The maximum current at any one output of the AD8383 is internally limited to 100 mA, average. In the event of a momen- tary short-circuit between a video output and a power supply rail (AVCC or AGND), the output current limit is sufficiently low to provide temporary protection ...

Page 6

... AVCCx Analog Power Supplies AGNDx Analog Supply Returns BYP Bypass STBY Standby NC 1 PIN 1 INDICATOR DB0 2 DB1 3 DB2 4 DB3 5 AD8383 DB4 6 TOP VIEW 7mm × 7mm DB5 7 (Not to Scale) DB6 8 DB7 9 DB8 10 DB9 CONNECT Figure 2. 48-Lead LFCSP Pin Configuration Description 10-Bit Data Input ...

Page 7

... Figure 3. Timing Diagram, Even Mode (E/O = HIGH) t CLK LOW V = 1.65V TH CLK SKEW SETUP HOLD V = 1.65V TH t SETUP STSQ t HOLD t SETUP XFR t HOLD Figure 4. Timing Diagram, Odd Mode (E/O = LOW) Rev Page CLK LOW V = 1.65V 1.65V TH t CLK HIGH V = 1.65V 1.65V TH AD8383 ...

Page 8

... AD8383 THEORY OF OPERATION TRANSFER FUNCTION AND ANALOG OUTPUT VOLTAGE The DecDriver has two regions of operation: where the video output voltages are either above or below a reference voltage VMID, and where VMID = (V1 + V2)/2. The transfer function defines the analog output voltage as the function of the digital input code as follows: ⎛ ...

Page 9

... The circuit in Figure 8 ensures symmetry to within 1 mV with a minimum component count. Bypass capacitors are not shown for clarity. The transfer function and the input symmetry error of the AD8383 are shown in Figure 9 when the circuit of Figure 8 is used to generate VBIAS. VCOM = 7V 820 ...

Page 10

... W for large capacitive loads, as shown in Table 4. Although the maximum safe operating junction temperature is higher, the AD8383 is 100% tested at a junction temperature of 125°C. Consequently, the maximum guaranteed operating junction temperature is 125°C. To limit the maximum junction ...

Page 11

... PCB requires thermal vias incorporated into the thermal pad design. Thermal performance increases logarithmi- cally with the number of vias, as shown in Figure 12. With the AD8383 on a standard JEDEC PCB, θ JA value when a total of 16 vias are used via count above 36, θ ...

Page 12

... PCB to be dissipated. Assuming there is no other heat-generating component near the AD8383, the thermal equivalent circuit of a system that consists of one AD8383 mounted on a PCB is shown in Figure 14. The thermal resistance of the top of the case, θ independent of the system variables, and well defined. θ ...

Page 13

... An alternative pattern that results in the maximum possible total power dissipation is a 1-pixel checkerboard pattern. The expected total power dissipation of the AD8383 Hz, 6-channel XGA projector displaying the 1-pixel-wide vertical line or checker- board pattern is 1.08 W (at AVCC = 15.5 V, VCOM = 7 V, and LCD capacitance = 150 pF) ...

Page 14

... AD8383 OUTLINE DIMENSIONS PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 9 AD8383ACPZ 0°C to 85° Pb-free part. 7.00 BSC SQ 0.60 MAX 37 36 6.75 TOP BSC SQ VIEW 0.50 0. 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 16. 48-Lead Frame Chip Scale Package [LFCSP] ...

Page 15

... NOTES Rev Page AD8383 ...

Page 16

... AD8383 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03191–0–1/04(0) Rev Page ...

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