pcf8576d NXP Semiconductors, pcf8576d Datasheet - Page 20

• Manufacturer Part Number: pcf8576d
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7
The I
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.
In chip-on-glass applications where the track resistance
from the SDA pad to the system SDA line can be
significant, a potential divider is generated by the bus
pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. It is therefore necessary to minimize the track
resistance from the SDA pad to the system SDA line to
guarantee a valid LOW-level during the acknowledge
cycle.
7.1
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this
time will be interpreted as a control signal (see Fig.13).
7.2
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P), (see Fig.14).
7.3
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’, (see Fig.15).
7.4
The number of data bytes that can be transferred from
transmitter to receiver between the START and STOP
conditions is unlimited. Each byte of eight bits is followed
by an acknowledge bit. The acknowledge bit is a
HIGH-level signal on the bus that is asserted by the
transmitter during which time the master generates an
extra acknowledge related clock pulse. An addressed
slave receiver must generate an acknowledge after
receiving each byte. Also a master receiver must generate
an acknowledge after receiving each byte that has been
clocked out of the slave transmitter. The acknowledging
device must pull-down the SDA line during the
2004 Dec 22
Universal LCD driver for low
multiplex rates
CHARACTERISTICS OF THE I
2
C-bus is for bidirectional, two-line communication
Bit transfer
Start and stop conditions
System configuration
Acknowledge
2
C-BUS
20
acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse (set-up and hold times must be taken into
consideration). A master receiver must signal an end of
data to the transmitter by not generating an acknowledge
on the last byte that has been clocked out of the slave.
In this event the transmitter must leave the data line HIGH
to enable the master to generate a STOP condition (see
Fig.16).
7.5
The PCF8576D acts as an I
not initiate I
master receiver. The only data output from the PCF8576D
are the acknowledge signals of the selected devices.
Device selection depends on the I
on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress
inputs A0, A1 and A2 are normally tied to V
defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are tied to V
accordance with a binary coding scheme such that no two
devices with a common I
same hardware subaddress.
7.6
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.7
Two I
are reserved for the PCF8576D. The least significant bit of
the slave address that a PCF8576D will respond to is
defined by the level tied to its SA0 input. The PCF8576D
is a write-only device and will not respond to a read
access. Having two reserved slave addresses allows the
following on the same I
The I
initiated with a START condition (S) from the I
master which is followed by one of two possible
PCF8576D slave addresses available. All PCF8576Ds
whose SA0 inputs correspond to bit 0 of the slave address
respond by asserting an acknowledge in parallel. This
I
inputs are set to the alternative level.
2
C-bus transfer is ignored by all PCF8576Ds whose SA0
Up to 16 PCF8576Ds for very large LCD applications
The use of two types of LCD multiplex drive.
2
2
C-bus protocol is shown in Fig.17. The sequence is
C-bus slave addresses (01110000 and 01110010)
PCF8576D I
Input filters
I
2
C-bus protocol
2
C-bus transfers or transmit data to an I
2
C-bus controller
2
C-bus:
2
C-bus slave address have the
2
C-bus slave receiver. It does
2
C-bus slave address,
Product specification
PCF8576D
SS
or V
SS
2
which
C-bus
DD
in
2
C-bus