pcf85162 NXP Semiconductors, pcf85162 Datasheet - Page 13

• Manufacturer Part Number: pcf85162
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF85162_1
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing
7.7 Display register
7.8 Segment outputs
7.9 Backplane outputs
The internal logic of the PCF85162 and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin V
as the clock signal for several PCF85162 in the system that are connected in cascade.
Pin CLK is enabled as an external clock input by connecting pin OSC to V
the LCD frame frequency is determined by the clock frequency (f
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state, which can damage the liquid crystals.
The PCF85162 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCF85162 in the system is
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD
frame frequency from the clock frequency. The frame frequency is a fixed division of the
clock frequency from either the internal or an external clock:
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs, and each column of the display RAM.
The LCD drive section includes 32 segment outputs S0 to S31 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display register. When
less than 32 segment outputs are required, the unused segment outputs should be left
open-circuit.
The LCD drive section includes four backplane outputs BP0 to BP3 which should be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
•
•
In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these
two adjacent outputs can be tied together to give enhanced drive capabilities.
In the 1:2 multiplex drive mode, BP0 and BP2 respectively BP1 and BP3 carry the
same signal. For increased drive capacity BP0 and BP2 respectively BP1 and BP3
may therefore be tied together.
SS
. If the internal oscillator is used, the output from pin CLK can be used
Rev. 01 — 7 January 2010
Universal LCD driver for low multiplex rates
f
fr
clk
=
).
f
-------
24
PCF85162
clk
© NXP B.V. 2010. All rights reserved.
DD
. In this case
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