pcf8523u/12aa/1 NXP Semiconductors, pcf8523u/12aa/1 Datasheet - Page 44

• Manufacturer Part Number: pcf8523u/12aa/1
• Description: Pcf8523 Real-time Clock Rtc And Calendar
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8523
Product data sheet
8.11.1 Bit transfer
8.11.2 START and STOP conditions
8.11.3 System configuration
8.11 I
The I
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines are
connected to a positive supply via a pull-up resistor. Data transfer is initiated only when
the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line remains
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the
STOP condition (P) (see
For this device a repeated START is not allowed. Therefore, a STOP has to be released
before the next START.
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master and the devices, which are
controlled by the master, are the slaves.
2
Fig 27. Bit transfer
Fig 28. Definition of START and STOP conditions
C-bus interface
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
START condition
All information provided in this document is subject to legal disclaimers.
SDA
SCL
S
Rev. 2 — 27 January 2011
Figure
28).
data valid
data line
stable;
Figure
27).
allowed
change
of data
Real-Time Clock (RTC) and calendar
STOP condition
mbc621
P
PCF8523
© NXP B.V. 2011. All rights reserved.
mbc622
SDA
SCL
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