pcf8548 NXP Semiconductors, pcf8548 Datasheet
pcf8548
Available stocks
Related parts for pcf8548
pcf8548 Summary of contents
Page 1
... DATA SHEET PCF8548 65 102 pixels matrix LCD driver Product specification Supersedes data of 1999 Mar 22 File under Integrated Circuits, IC12 INTEGRATED CIRCUITS 1999 Aug 16 ...
Page 2
... C-bus data lines C-bus 2 Product specification PCF8548 INSTRUCTIONS External reset (RES) Function set Power-Down (PD Display control D and E Display configuration TRS BRS Set Y address of RAM Set X address of RAM Set HV generator stages S[1:0] Temperature control ...
Page 3
... The PCF8548 interfaces to most microcontrollers via C-bus interface 3.1 LCD SS The PCF8548 is available as chip with bumps in tray; tape carrier package is available on request. LCD PACKAGE DESCRIPTION chip with bumps in tray quarter wafer 3 APPLICATIONS GENERAL DESCRIPTION Packages Product specifi ...
Page 4
... LCD row driver outputs 198 to 211 LCD row driver outputs 212 to 215 test outputs 216 oscillator 217 test input 218 to 223 supply voltage 1 224 to 226 supply voltage 3 227 to 233 supply voltage 2 27, 55, 56, dummy pads 196 and 197 PCF8548 OSC ...
Page 5
... An external LCD supply voltage can be supplied using the V pad. In this case, V LCDIN to be connected to ground, and the internal voltage generator has to be programmed to zero. If the PCF8548 is in power-down mode, the external LCD supply voltage must be switched off. 7 LCD power supply LCDOUT Positive power supply for the liquid crystal display ...
Page 6
... external DD1 8.6 LCD row and column drivers The PCF8548 contains 65 row and 102 column drivers, which connect the appropriate LCD bias voltages to the display in accordance with the data to be displayed. Figure 2 shows typical waveforms. Unused outputs should be left unconnected. ...
Page 7
... V (t) = C1(t) R0(t). state1 V (t) = C1(t) R1(t). state2 1999 Aug 16 frame n frame n ... 8... Fig.2 Typical LCD driver waveforms. 7 Product specification PCF8548 1 V state1 (t) V state2 ( LCD LCD ...
Page 8
... Philips Semiconductors 65 102 pixels matrix LCD driver bank 0 bank 1 bank 2 bank 3 bank 7 bank 8 1999 Aug 16 DDRAM MGS395 Fig.3 DDRAM to display mapping. 8 Product specification PCF8548 top of LCD LCD ...
Page 9
... LCD driver 10 ADDRESSING The Display Data RAM (DDRAM) of the PCF8548 is accessed as indicated in Figs and 9. The DDRAM has a matrix of 65 102 bits. The RAM cells are addressed by the X and Y address pointers. The address ranges are X0 to X101 (1100101b) and (1000b). Addresses outside of these ranges are not allowed. In vertical addressing mode ( the Y address increments after each byte (see Fig ...
Page 10
... The DO bit defines the bit order (MSB on top or MSB on bottom) for writing to the RAM (see Figs 6 and 7). MSB handbook, full pagewidth LSB MSB LSB 1999 Aug 16 X address Fig.6 RAM byte organization Product specification PCF8548 0 Y address 917 8 101 MGS397 MGS398 ...
Page 11
... Fig.9). When the mirroring is disabled and the address located at the left side (column 0) of the display (see Fig.8). handbook, full pagewidth 1999 Aug 16 Fig.7 RAM byte organization address Y address Fig.8 RAM format addressing (MX = 0). 11 Product specification PCF8548 MGS399 0 8 101 MGS400 ...
Page 12
... LCD driver handbook, full pagewidth 10.2 RAM access If the D/C bit is logic 1 the RAM can be written to. The data is written to the RAM during the acknowledge cycle. 1999 Aug 16 101 X address Y address Fig.9 RAM format addressing (MX = 1). 12 Product specification PCF8548 MBL044 ...
Page 13
... In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I in Fig.13. data line change stable; of data allowed data valid Fig.10 Bit transfer. 13 Product specification PCF8548 A CKNOWLEDGE 2 C-bus is illustrated MBC621 ...
Page 14
... Aug 16 Fig.11 Definition of START and STOP conditions. SLAVE SLAVE TRANSMITTER/ RECEIVER RECEIVER Fig.12 System configuration START condition Fig.13 Acknowledgement on the I 14 Product specification PCF8548 SDA SCL P STOP condition MBC622 MASTER MASTER TRANSMITTER/ TRANSMITTER RECEIVER MGA807 not acknowledge acknowledge 8 9 ...
Page 15
... The data pointer is automatically updated and the data is directed to the ) or SS1 intended PCF8548 device. If the D/C bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed slave ...
Page 16
... LCD driver 12 INSTRUCTIONS The instruction format is divided into two modes D/C is set LOW, commands can be sent to the chip D/C is set HIGH, the DDRAM will be accessed. Every instruction can be sent in any order to the PCF8548. Table 1 Instruction set INSTRUCTION D/C R ...
Page 17
... X address is mirrored display is vertically mirrored top rows are mirrored bottom rows are mirrored LSB is on top V programming range HIGH LCD [6: and PRS = Product specification PCF8548 1 RESET STATE ...
Page 18
... Bit TRS enables the top row pad blocks to be mirrored. This is used to enable flexibility in the wiring of the row lines from the PCF8548 to the LCD cell (e.g. COG or TCP wiring). When TRS = 0 rows and rows are organized as illustrated in Fig.22. When TRS = 1 rows and rows are mirrored and organized as illustrated in Fig ...
Page 19
... Aug 16 There are 4 different temperature coefficients available in the PCF8548 (see Fig.15). The coefficients are selected by the two bits TC[1:0]. Table 6 shows the typical values of the different temperature coefficients. The coefficients are proportional to the programmed V 12.9 ...
Page 20
... DD2 ranges are selectable via the LCD and for the HIGH (PRS = 1) range [6;0] and bit PRS are all set 6. -------------------------------------- - = – ---------- 65 is the threshold voltage of the liquid crystal PCF8548 with steps 2 th UNIT ...
Page 21
... V remains below 9.0 V. LCD 1999 Aug 5FH 6FH 7FH 00H 01H 02H 03H 04H 05H 06H Fig.16 V programming of PCF8548. OP allows values above the maximum allowed V LCD register and selecting the temperature coefficient, under all conditions and OP 21 Product specification PCF8548 ...
Page 22
... V LCD with internal V generation; LCD 7.6 V; DD1 LCD sclk amb display load; 4 charge pump; notes 2 and 3 22 Product specification PCF8548 = 0 V. Stress above one or SS MIN. MAX. 0.5 +6.5 0.5 +4.5 0.5 +9.0 50 + +10 10 +10 300 30 = 4.5 to 9.0 V ...
Page 23
... Product specification MIN. TYP. 200 1 SS1 0.7V DD1 100 0 100 0 300 C), maximum tolerance values are measured PCF8548 MAX. UNIT 350 0.3V V DD1 V V DD1 + 100 mV 100 mV 300 ...
Page 24
... V and V with an input voltage swing The rise and fall times specified here refer to the driver device (i.e. not PCF8548) and are part of the general fast 2 I C-bus specification. When PCF8548 asserts an acknowledge on SDA, the minimum fall time capacitive load per bus line. ...
Page 25
... Philips Semiconductors 65 102 pixels matrix LCD driver 17 RESET handbook, full pagewidth V DD RES V DD RES 1999 Aug 16 t W(RES) t VHRL t W(RES) Fig.17 Reset timing. 25 Product specification PCF8548 t W(RES) t W(RES) MGS404 ...
Page 26
... Philips Semiconductors 65 102 pixels matrix LCD driver 18 APPLICATION INFORMATION Table 7 Programming example for PCF8548 STEP C-bus start C-bus start ...
Page 27
... Product specification PCF8548 DISPLAY OPERATION data write MGS407 data write MGS408 data write MGS409 data write MGS410 data write MGS411 restart slave address for write control byte with set Co bit and D/C set to logic 0 display control ...
Page 28
... SCL V DD1 PCF8548 SDAIN SDAOUT 2 Fig.18 Connecting the I C-bus interface. 28 Product specification PCF8548 DISPLAY OPERATION control byte with set Co bit and D/C set to logic 1 data write MGS414 control byte with cleared Co bit and D/C set to logic 0 set X address of RAM; set address to ‘0000000’ ...
Page 29
... Fig.20 Internal charge pump is used and two separate supply voltages. 1999 Aug 16 DISPLAY 102 32 102 PCF8548 3 C VDD I DISPLAY 102 65 32 102 PCF8548 3 C VDD1 V DD1 I/O C VDD2 V DD2 VLCD MGS418 33 C VLCD MGS419 Product specification PCF8548 ...
Page 30
... The number of I/Os depends on the application. The pinning of the PCF8548 is optimized for single plane wiring e.g. for chip-on-glass display modules, or for TCP. Display size: 65 102 pixels. The required minimum value for the external capacitors in an application with the PCF8548 ...
Page 31
... R17 74 3850 R18 75 3780 C0 76 3570 C1 77 3500 C2 78 3430 C3 79 3360 C4 80 3290 Product specification PCF8548 y +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899 ...
Page 32
... C82 158 +2380 C83 159 +2450 C84 160 +2520 C85 161 +2590 C86 162 +2660 C87 163 +2730 C88 164 +2800 PCF8548 y 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899.4 899 ...
Page 33
... DD2 V 231 +1560 DD2 V 232 +1480 DD2 V 233 +1400 DD2 x y +5214 899.4 5214 899.4 +4099 +899.4 4099 +899.4 PCF8548 y +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899.4 +899 ...
Page 34
Acrobat reader. white to force landscape pages to be ... Maximum chip size: 2.12 mm 10.99 mm. PC8548 Fig.22 Bonding ...
Page 35
... LCD driver handbook, full pagewidth R64 R63 . . . . . R52 R51 TRS = 1 R19 R20 . . . . . R31 R32 1999 Aug C100 C101 MGS657 Fig.23 Pad layout for BRS, TRS and MX. 35 Product specification PCF8548 R50 R49 . . . . . R34 R33 BRS = R17 R18 ...
Page 36
... V LCDIN V SS1 V LCDOUT V LCDSENSE V SS1 COL 0-101/ ROW 0-64 V DD1 SA0 OSC RES SS1 T8 V SS1 Fig.24 Device protection diagram. 36 Product specification PCF8548 V DD1 T2 V SS1 V DD1 T3 SS1 V LCDIN T9 T10 T11 T12 V SS1 V LCDIN 1 per block V SS1 MGS422 ...
Page 37
... Fig.25 Tray details. Table 10 Dimensions DIM PC8548 MGS424 37 Product specification PCF8548 MGS423 DESCRIPTION pocket pitch, x direction pocket pitch, y direction pocket width, x direction pocket width, y direction tray width, x direction tray width, x direction number of pockets in x direction number of pockets in ...
Page 38
... It is the responsibility of the customer to test and qualify their application in which the die is used. 1999 Aug 16 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 38 Product specification PCF8548 2 C patent to use the 2 C specification defined by ...
Page 39
... Philips Semiconductors 65 102 pixels matrix LCD driver 1999 Aug 16 NOTES 39 Product specification PCF8548 ...
Page 40
Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...