pca85232 NXP Semiconductors, pca85232 Datasheet - Page 24

• Manufacturer Part Number: pca85232
• Description: Pca85232 Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA85232
Product data sheet
7.16.4 I
7.16.5 Input filters
7.16.6 I
The PCA85232 acts as an I
transmit data to an I
the acknowledge signals from the selected devices. Device selection depends on the
I
subaddress.
In single device applications, the hardware subaddress inputs A0 and A1 are normally tied
to V
A0 and A1 are tied to V
two devices with a common I
To enhance noise immunity in electrical adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
Two I
PCA85232.The entire I
Table 7.
The PCA85232 is a write-only device and will not respond to a read access, therefore bit 0
should always be logic 0. Bit 1 of the slave address byte, that a PCA85232 will respond to,
is defined by the level tied to its SA0 input (V
Having two reserved slave addresses allows the following on the same I
The I
condition (S) from the I
slave addresses available. All PCA85232 with the corresponding SA0 level acknowledge
in parallel to the slave address, but all PCA85232 with the alternative SA0 level ignore the
whole I
Bit
2
2
2
C-bus slave address, on the transferred command data, and on the hardware
•
•
C-bus controller
C-bus protocol
SS
Up to 8 PCA85232 on the same I
The use of two types of LCD multiplex on the same I
2
2
C-bus protocol is shown in
C-bus slave addresses (0111 000 and 0111 001) are reserved for the
which defines the hardware subaddress 0. In multiple device applications
2
C-bus transfer.
Slave address
7
MSB
0
I
2
C slave address byte
All information provided in this document is subject to legal disclaimers.
2
6
1
C-bus master receiver. The only data output from the PCA85232 are
Rev. 1 — 8 December 2010
2
2
SS
C-bus master which is followed by one of two possible PCA85232
C-bus slave address byte is shown in
or V
2
C-bus slave receiver. It does not initiate I
2
C-bus slave address have the same hardware subaddress.
DD
5
1
in accordance with a binary coding scheme such that no
Figure
2
C-bus for very large LCD applications
4
1
17. The sequence is initiated with a START
SS
for logic 0 and V
3
0
LCD driver for low multiplex rates
2
C-bus
2
0
Table
DD
for logic 1).
PCA85232
7.
2
1
SA0
C-bus transfers or
© NXP B.V. 2010. All rights reserved.
2
C-bus:
0
LSB
R/W
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