pca8534a NXP Semiconductors, pca8534a Datasheet
pca8534a
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pca8534a Summary of contents
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... Universal LCD driver for low multiplex rates Rev. 02 — 1 June 2010 1. General description The PCA8534A is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and segments. It can be easily cascaded for larger LCD applications. The PCA8534A is compatible with most ...
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... NXP Semiconductors 3. Ordering information Table 1. Type number PCA8534AH/Q900 LQFP80 plastic low profile quad flat package; 4. Marking Table 2. Type number PCA8534AH/Q900 PCA8534A_2 Product data sheet Ordering information Package Name Description 80 leads; body 12 × 12 × 1.4 mm Marking codes All information provided in this document is subject to legal disclaimers. ...
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... LCD LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR SCL INPUT FILTERS SDA Fig 1. Block diagram of PCA8534A PCA8534A_2 Product data sheet BP0 BP1 BP2 BP3 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROL PCA8534A BLINKER TIMEBASE COMMAND POWER-ON ...
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... PCA8534AH Top view. For mechanical details, see Pin configuration for LQFP80 (PCA8534AH) All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates Figure 24. 60 S10 ...
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... LCD supply voltage output LCD segment output All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The possible display configurations of the PCA8534A depend on the number of active backplane outputs required. A selection of display configurations is shown in of these configurations can be implemented in the typical system shown in Table 4 ...
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... V LCD 2 × All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates 2 C-bus after a power-on for at least allow and V . The center resistor is bypassed LCD SS Table ...
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... LCD LCD off RMS is sometimes referred as the LCD operating voltage. LCD All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates to V and is determined from off(RMS) × 2.449V = ( ) ...
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... V (t). state2 ( BP0 off(RMS) Static drive mode waveforms All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates Figure T fr LCD segments state 1 state 2 (on) (off) mgl745 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA8534A allows the use of Figure 6. Fig 5. PCA8534A_2 Product data sheet ⁄ 1 bias LCD BP0 LCD LCD BP1 LCD LCD ...
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... BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:2 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms mgl747 at LCD segment ...
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... BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:3 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (b) Resultant waveforms mgl748 at LCD segment. ...
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... Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:4 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates T fr state 1 state 2 mgl749 at LCD segment. ⁄ 1 bias 3 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCA8534A are timed by the frequency f , which equals either the built-in oscillator frequency f clk f . The clock frequency f clk(ext) 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin V output from pin CLK is the clock signal for any cascaded PCA8534A in the system. ...
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... BP3 respectively. Fig 9. When display data is transmitted to the PCA8534A the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples or quadruples ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... Then the data pointer is set to the preferred display RAM address by sending the load-data-pointer command. Once the display RAM of the first PCA8534A has been written, the second PCA8534A is selected by sending the device-select command again. This time however the command matches the second device's hardware subaddress ...
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... NXP Semiconductors This last step is very important because during writing data to the first PCA8534A, the data pointer of the second PCA8534A is incremented. In addition, the hardware subaddress should not be changed whilst the device is being accessed on the I interface. 7.13 Output bank selector The output bank selector (see address for transfer to the display register ...
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... Table 2 C-bus SDA SCL data line stable; data valid All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates Blink frequency Blinking off 0.5 Hz 11). Figure 11). change of data ...
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... Product data sheet Figure 12). S START condition MASTER SLAVE TRANSMITTER/ RECEIVER RECEIVER All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates P STOP condition Figure 13). SLAVE MASTER TRANSMITTER/ TRANSMITTER RECEIVER SDA ...
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... C-bus 2 C-bus slave receiver. It does not initiate I 2 C-bus master receiver. The only data output from the PCA8534A are which defines the hardware subaddress 0. In multiple device SS 2 C-bus slave address have the same hardware 2 C-bus slave address byte is shown in ...
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... NXP Semiconductors The PCA8534A is a write-only device and will not respond to a read access, therefore bit 0 should always be logic 0. Bit 1 of the slave address byte that a PCA8534A will respond to, is defined by the level tied to its SA0 input (V Having two reserved slave addresses allows the following on the same I • ...
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... Both data pointer and subaddress counter are automatically updated. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCA8534A. After the last display byte, the I Alternatively a START may be issued to RESTART I 7.17 Command decoder The command decoder identifies command bytes that arrive on the I five commands: Table 10 ...
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... LCD display data 0 RAM bit 0 1 RAM bit 2 All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates 1:2 multiplex RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 © ...
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... The blink frequencies are shown in 7.18 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCA8534A and coordinates their effects. The controller also loads display data into the display RAM as required by the storage order. ...
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... A0, A1 LCD BP0, BP1, BP2, BP3 LCD S0 to S59 V SS All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A SCL V SS SDA LCD V SS 001aah615 © NXP B.V. 2010. All rights reserved. ...
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... Ref. 8 “JESD78” All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates ) is off, or vice versa. This may cause unwanted DD and V must be applied or removed together. ...
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... V LCD sgm LCD external clock with 50 % duty factor All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates ° +85 C; unless otherwise specified. Min 1.8 2.5 [1][2] - [1][3] - − 0.5 V ...
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... T = 1.536 kHz; all RAM written with logic 1; no display connected. amb clk(ext) with respect to V DD(LCD) All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates 001aal523 ( 1.536 kHz ...
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... Conditions LCD . All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates ° +85 C; unless otherwise specified. Min Typ [1] 960 1536 797 1536 130 - ...
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... CLK SYNC t PD(SYNC_N BUF LOW t HD;STA 2 C-bus timing waveforms All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates t clk(L) t PD(SYNC_N) t SYNC_NL t PD(drv HD;DAT t HIGH t SU ...
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... NXP Semiconductors 12. Application information 12.1 Cascaded operation Large display configurations PCA8534A can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable 2 I C-bus slave address (SA0). Table 19. Cluster cascaded PCA8534A are synchronized, they can share the backplane signals from one of the devices in the cascade ...
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... A PCA8534A asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost restored by the first PCA8534A to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal ...
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... Number of devices The PCA8534A can always be cascaded with other devices of the same type or conditionally with other devices of the same family. This allows optimal drive selection for a given number of pixels to display. synchronization signals. PCA8534A_2 Product data sheet ...
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... OSC connected to V must be ensured that the clock tree is designed such that on all PCA8534A the clock propagation delay from the clock source to all PCA8534A in the cascade is as equal as possible since otherwise synchronization artefacts may occur. ...
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... 0.27 0.18 12.1 12.1 14.15 14.15 0.5 0.13 0.12 11.9 11.9 13.85 13.85 REFERENCES JEDEC JEITA MS-026 All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates detail 0.75 1.45 1 0.2 0.15 0.1 0.30 1.05 EUROPEAN PROJECTION ...
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... Inspection and repair • Lead-free soldering versus SnPb soldering PCA8534A_2 Product data sheet Universal LCD driver for low multiplex rates All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A © NXP B.V. 2010. All rights reserved ...
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... Volume (mm ) < 350 260 260 250 Figure 25. All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates Figure 25) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 ...
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... MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates peak temperature © NXP B.V. 2010. All rights reserved. time 001aac844 ...
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... Resistance and Capacitance Root Mean Square Serial Clock Line Serial DAta line Surface-Mount Device All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... Universal LCD driver for low multiplex rates 2 C-bus specification and user manual Data sheet status Product data sheet Table 2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Change notice Supersedes - PCA8534A_1 - - © NXP B.V. 2010. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 02 — 1 June 2010 PCA8534A Universal LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... Package outline Handling information . . . . . . . . . . . . . . . . . . . 37 Soldering of SMD packages . . . . . . . . . . . . . . 37 Introduction to soldering Wave and reflow soldering Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 38 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 38 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40 References Revision history . . . . . . . . . . . . . . . . . . . . . . . 41 Legal information . . . . . . . . . . . . . . . . . . . . . . 42 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Contact information . . . . . . . . . . . . . . . . . . . . 43 Contents Date of release: 1 June 2010 Document identifier: PCA8534A_2 All rights reserved. ...