m41t00s STMicroelectronics, m41t00s Datasheet - Page 10

• Manufacturer Part Number: m41t00s
• Description: Serial Access Real-time Clock
• Manufacturer: STMicroelectronics

M41T00S
WRITE Mode
In this mode the master transmitter transmits to
the M41T00S slave receiver. Bus protocol is
shown in Figure 10. Following the START condi-
tion and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T00S slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see
ceived the word address and each data byte.
Figure 10. WRITE Mode Sequence
10/23
Figure 7., page 8
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
S
and again after it has re-
ADDRESS
SLAVE
ADDRESS (An)
WORD
Data Retention Mode
With valid V
cessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the pow-
er input will be switched from the V
battery when V
Switchover Voltage (V
registers will be maintained by the attached bat-
tery supply. On power-up, when V
nominal value, write protection continues for t
For a further, more detailed review of lifetime cal-
culations, please see Application Note AN1012.
DATA n
CC
DATA n+1
CC
applied, the M41T00S can be ac-
falls below the Battery Back-up
SO
). At this time the clock
DATA n+X
AI00591
CC
CC
returns to a
pin to the
P
REC
.