m41t00cap STMicroelectronics, m41t00cap Datasheet - Page 13

• Manufacturer Part Number: m41t00cap
• Description: Serial Access Real-time Clock With Integral Backup Battery
• Manufacturer: STMicroelectronics

M41T00CAP
3.8
Figure 9.
3.9
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
WRITE mode
In this mode the master transmitter transmits to the M41T00CAP slave receiver. Bus
protocol is shown in
(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The device slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
and again after it has received the word address and after each data byte.
WRITE mode sequence
Data retention mode
With valid V
or WRITE cycles. Should the supply voltage decay, the power input will be switched from the
V
this time the clock registers will be maintained by the internal battery supply. On power-up,
when V
above V
CC
pin to the battery when V
CC
SO
S
returns to a nominal value, write protection continues for t
.
ADDRESS
CC
SLAVE
applied, the M41T00CAP can be accessed as described above with READ
Figure
ADDRESS (An)
9. Following the START condition and slave address, a logic '0'
WORD
CC
falls below the battery backup switchover voltage (V
DATA n
DATA n+1
REC
DATA n+X
after V
AI00591
CC
Operation
rises
P
SO
13/27
). At