m41st84w STMicroelectronics, m41st84w Datasheet - Page 10

• Manufacturer Part Number: m41st84w
• Description: 3.0/3.3v I 2c Serial Rtc With Supervisory Functions
• Manufacturer: STMicroelectronics

M41ST84W
READ Mode
In this mode the master reads the M41ST84W
slave after setting the slave address (see
9., page
Bit (R/W=0) and the Acknowledge Bit, the word
address ‘An’ is written to the on-chip address
pointer. Next the START condition and slave ad-
dress are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an Acknowledge Bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41ST84W slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new
incremented to “An+2.”
Figure 9. Slave Address Location
10/29
byte
10). Following the WRITE Mode Control
and
the
START
address
pointer
1
Figure
1
SLAVE ADDRESS
0
is
1
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see
10., page
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41ST84W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one
11., page
0
0
stored
0
R/W
11).
11).
A
in
AI00602
the
pointer
(see
Figure
Figure