m41st84w STMicroelectronics, m41st84w Datasheet - Page 12

• Manufacturer Part Number: m41st84w
• Description: 3.0/3.3v I 2c Serial Rtc With Supervisory Functions
• Manufacturer: STMicroelectronics

M41ST84W
WRITE Mode
In this mode the master transmitter transmits to
the M41ST84W slave receiver. Bus protocol is
shown in
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST84W slave receiver will send an
acknowledge clock to the master transmitter after
it has received the slave address (see
9., page
word address and each data byte.
Figure 12. WRITE Mode Sequence
12/29
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
10) and again after it has received the
Figure 12., page
S
ADDRESS
SLAVE
12. Following the
ADDRESS (An)
WORD
Figure
Data Retention Mode
With valid V
cessed as described above with READ or WRITE
cycles. Should the supply voltage decay, the
M41ST84W will automatically deselect, write pro-
tecting itself when V
and V
inhibiting access to the clock registers. At this
time, the Reset pin (RST) is driven active and will
remain active until V
When V
Switchover Voltage (V
from the V
clock registers and SRAM are maintained from the
attached battery supply.
All outputs become high impedance. On power up,
when V
tion continues for t
mains active during this time (see
19., page
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
DATA n
PFD
CC
CC
(min). This is accomplished by internally
25).
returns to a nominal value, write protec-
CC
CC
falls below the Battery Back-up
pin to the external battery, and the
DATA n+1
applied, the M41ST84W can be ac-
rec
CC
CC
SO
. The RST signal also re-
returns to nominal levels.
falls between V
), power input is switched
DATA n+X
AI00591
PFD
Figure
(max)
P