max5961 Maxim Integrated Products, Inc., max5961 Datasheet - Page 30

• Manufacturer Part Number: max5961
• Description: 0 To 16v, Quad, Hot-swap Controller With 10-bit Current And Voltage Monitor
• Manufacturer: Maxim Integrated Products, Inc.

0 to 16V, Quad, Hot-Swap Controller
with 10-Bit Current and Voltage Monitor
The PG_ output for a given channel is asserted when
the voltage at MON_ is between the undervoltage and
overvoltage critical limits. The status of the power-good
signals is maintained in register status3[3:0]. A value of
1 in any of the pg[] bits indicates a power-good condi-
tion, regardless of the POL setting, which only affects
the PG_ output polarity. The open-drain PG_ output can
be configured for active-high or active-low status indi-
cation by the state of the POL input (see Table 30).
30
Table 30. status3 Register Format
Table 31a. Power-Good Assertion Delay-Time Register Format
Table 31b. Power-Good Assertion Delay
Description:
Register Title:
Register Address:
Description:
Register Title:
Register Address:
Ch4_dly1
______________________________________________________________________________________
bit 7
bit 7
R/W
R
Power-Good Detection and PG_ Outputs
Chx_dly1
0
0
1
1
Ch4_dly0
RETRY
bit 6
bit 6
R/W
R
Power-good status register; RETRY, POL, and alert bits
status3
0x62
Power-good assertion delay-time register
pgdly
0x66
Ch3_dly1
POL
bit 5
bit 5
R
R/W
Ch3_dly0
alert
bit 4
R/W
Chx_dly0
bit 4
R/W
0
1
0
1
pg[4]
bit 3
Ch2_dly1
R
bit 3
R/W
The POL input sets the value of bit 5 of the status3 reg-
ister, which is a read-only bit; the state of the POL input
can be changed at any time during operation and the
polarity of the PG_ outputs will change accordingly.
The assertion of the PG_ output is delayed by a user-
selectable time delay of 50ms, 100ms, 200ms, or
400ms (see Tables 31a and 31b).
pg[3]
bit 2
Ch2_dly0
R
bit 2
R/W
PG_ ASSERTION DELAY (ms)
pg[2]
Ch1_dly1
bit 1
R
bit 1
R/W
100
200
400
50
Ch1_dly0
pg[1]
bit 0
R
R/W
bit 0
VALUE
RESET
RESET
VALUE
0x00
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