max5134 Maxim Integrated Products, Inc., max5134 Datasheet - Page 10

• Manufacturer Part Number: max5134
• Description: Low-power, Quad 16-bit, Buffered Voltage-output Dac
• Manufacturer: Maxim Integrated Products, Inc.

Low-Power, Quad 16-Bit,
Buffered Voltage-Output DAC
The external reference input features a typical input
impedance of 113kΩ and accepts an input voltage
from +2V to AVDD. Connect an external voltage
supply between REFI and GND to apply an ex-
ternal reference. Leave REFO unconnected. Visit
www.maxim-ic.com/products/references for a list of
available external voltage-reference devices.
Connect AVDD to REFI to use AVDD as the reference
voltage. Leave REFO unconnected.
The MAX5134 3-wire serial interface is compatible with
MICROWIRE, SPI, QSPI, and DSPs (Figures 2, 3). The
interface provides three inputs, SCLK, CS, and DIN and
one output, READY. Use READY to verify communica-
tion or to daisy-chain multiple devices (see the READY
section). READY is capable of driving a 20pF load with
a 30ns (max) delay from the falling edge of SCLK. The
chip-select input (CS) frames the serial data loading at
DIN. Following a chip-select input’s high-to-low transi-
Table 1. Operating Mode Truth Table
10
C7 C6 C5 C4 C3
MSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
______________________________________________________________________________________
0
0
0
0
0
0
1
1
CONTROL BITS
0
0
0
0
0
1
1
0
DAC
DAC
0
0
0
0
0
3
3
0
DAC
DAC
C2
0
0
0
0
1
2
2
0
DAC
DAC
C1
0
0
1
1
0
1
1
0
DAC
DAC
C0 D15 D14 D13 D12 D11 D10 D9
0
1
0
1
1
0
0
0
D15 D14 D13 D12 D11 D10 D9
D15 D14 D13 D12 D11 D10 D9
X
X
X
X
0
X
AVDD as Reference
External Reference
Serial Interface
24-BIT WORD
X
X
X
X
0
X
X
X
X
X
0
X
X
X
X
X
0
X
DAC
DAC
X
3
X
3
0
X
DATA BITS
DAC
DAC
X
2
X
2
0
X
DAC
DAC
LIN
X
X
X
1
1
tion, the data is shifted synchronously and latched into
the input register on each falling edge of the serial-
clock input (SCLK). Each serial word is 24 bits. The first
8 bits are the control word followed by 16 data bits
(MSB first), as shown in Table 1. The serial input regis-
ter transfers its contents to the input registers after
loading 24 bits of data. To initiate a new data transfer,
drive CS high, keep CS high for a minimum of 33ns
before the next write sequence. The SCLK can be
either high or low between CS write pulses. Figure 1
shows the timing diagram for the complete 3-wire serial-
interface transmission.
The MAX5134 digital inputs are double buffered.
Depending on the command issued through the serial
interface, the input register(s) can be loaded without
effecting the DAC register(s) using the write command.
To update the DAC registers, either pulse the LDAC input
low to asynchronously update all DAC outputs, or use the
software LDAC command. Use the write through com-
mands (see Table 1) to update the DAC outputs immedi-
ately after the data is received. Only use the write through
command to update the DAC output immediately.
DAC
DAC
D8
D8
D8
X
X
X
0
0
0
READY_EN
D7
D7
D7
X
X
X
X
0
D6–D0
LSB
D6
D6
X
X
X
X
X
0
Linearity Optimize DAC linearity.
Through
Control
DESC
Power
LDAC
Write
Write
NOP
NOP
CLR
No operation.
Move contents of input
to DAC registers
indicated by 1’s. No
effect on registers
indicated by 0’s.
Software clear.
Power down DAC’s
indicated by 1’s.
Set READY_EN = 1 to
enable READY.
Write to selected input
registers (DAC output
not affected).
Write to selected input
and DAC registers, DAC
outputs updated (write
through).
No operation.
FUNCTION