max5134 Maxim Integrated Products, Inc., max5134 Datasheet - Page 12

• Manufacturer Part Number: max5134
• Description: Low-power, Quad 16-bit, Buffered Voltage-output Dac
• Manufacturer: Maxim Integrated Products, Inc.

Low-Power, Quad 16-Bit,
Buffered Voltage-Output DAC
Daisy chain multiple MAX5134 devices by connecting
the first device conventionally, then connect its READY
output to the CS of the following device. Repeat for any
other devices in the chain, and drive the SCLK and DIN
lines in parallel (Figure 5). When sending commands to
daisy-chained MAX5134s, the devices are accessed
serially starting with the first device in the chain. The first
24 data bits are read by the first device, the second 24
data bits are read by the second device and so on
(Figure 4). Figure 6 shows the configuration when CS is
not driven by the µC.
To perform a daisy-chain write operation, drive CS low
and output the data serially to DIN. The propagation of
the READY signal then controls how the data is read by
each device. As the data propagates through the daisy
chain, each individual command in the chain is execut-
ed on the 24th falling clock edge following the falling
edge of the respective CS input. To update just one
device in a daisy chain, send the no-op command to
the other devices in the chain.
If READY is not required, write command 0x03 (power
control) and set READY_EN = 0 (see Table 1) to dis-
able the READY output.
The MAX5134 features a software clear command
(0x02). The software clear command acts as a software
POR, erasing the contents of all registers. All outputs
return to the state determined by the M/Z input.
Figure 5. Daisy-Chain Configuration
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μC
MOSI
SCK
I/O
Clear Command
DIN
SCLK
CS
SLAVE 1
READY
The MAX5134 features a software-controlled individual
power-down mode for each channel. The internal refer-
ence and biasing circuits power down to conserve
power when all 4 channels are powered down. In
power-down, the outputs disconnect from the buffers
and are grounded with an internal 80kΩ resistor. The
DAC register holds the retained code so that the output
is restored when the channel powers up. The serial
interface remains active in power-down mode.
The MAX5134 features an active-low LDAC logic input
that allows the outputs to update asynchronously. Keep
LDAC high during normal operation (when the device is
controlled only through the serial interface). Drive LDAC
low to simultaneously update all DAC outputs with data
from their respective input registers. Figure 7 shows the
LDAC timing with respect to OUT_. Holding LDAC low
causes the input registers to become transparent and
data written to the DAC registers to immediately update
the DAC outputs. A software command can also acti-
vate the LDAC operation. To activate LDAC by software,
set control word 0x01 and data bits A11–A8 to select
which DAC to load, and all other data bits to don’t care.
See Table 1 for the data format. This operation updates
only the DAC outputs that are flagged with a “1”.
DAC outputs flagged with a “0” remain unchanged.
DIN
SCLK
CS
SLAVE 2
READY
Load DAC ( LDAC ) Input
Power-Down Mode
DIN
SCLK
CS
SLAVE 3
READY