lm9820ccwmx National Semiconductor Corporation, lm9820ccwmx Datasheet - Page 6

• Manufacturer Part Number: lm9820ccwmx
• Description: 10/12-bit Image Sensor Processor Analog Front End
• Manufacturer: National Semiconductor Corporation

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,
but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND=
Note 3: When the input voltage (V
maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
able power dissipation at any temperature is P
is 84°C /W for the M20B SOIC package
Note 5: Human body model, 100pF capacitor discharged through a 1.5k resistor.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear
Data Book for other methods of soldering surface mount devices.
AC Electrical Characteristics
The following specifications apply for
limits apply for T
t
Symbol
SampCLK
t
t
t
t
t
SampSU
SCLKLA
LASCLK
SampLo
t
SampHi
t
t
t
f
t
t
t
MCLK
SCNL
SCLK
LANL
MCLK
DDO
HDO
DSU
t
t
DH
LA
Maximum
MCLK
MCLK
SampCLK
falling edge
SampCLK
Low time for
High time for
SampCLK
edge of
falling edge of
data
hold time of current data from falling
edge of
D2
Input data setup time before
D2
Input data hold time after
rising edge
D2
before
D1
D2
High time for
D1
falling edge
(SCLK) Serial Clock Period
(SCLK) rising edge
(SCLK) rising edge after bit B0
(Latch) rising edge before next
(SCLK) rising edge
(Latch) rising edge before
A
=T
Duty Cycle
period
J
D1
=T
MCLK
MCLK
IN
falling edge before
period
falling edge before rising
(Latch) rising edge
MIN
MCLK
) at any pin exceeds the power supplies (V
.
SampCLK
Parameter
to T
SampCLK
D1
MCLK
(Latch)
Frequency
MAX
D
= (T
before new valid
; all other limits T
AGND
J
max - T
D2
AGND
=
(SCLK)
DGND
NewLine
NewLine
A
) /
=
DGND
JA
=0V,
. T
J
A
max = 150°C for this device. The typical thermal resistance (
=0V, unless otherwise specified.
=T
VA
=
J
=25°C. (Notes 7 & 8)
VD
IN
=+5.0V
<GND or V
Conditions
6
DC
IN
, f
>VA or VD), the current at that pin should be limited to 25mA. The 50mA
MCLK
=24MHz,
J
max,
(Note 9)
Typical
JA
t
MCLK
and the ambient temperature, T
41
50
50
1
=1/f
MCLK
(Note 10)
, t
Limits
r
=t
JA
24
40
60
40
15
3
4
4
0
3
3
3
3
3
f
) of this part when board mounted
=5ns, R
http://www.national.com
s
A
=25 . Boldface
. The maximum allow-
t
t
t
t
MHz (min)
MCLK
MCLK
MCLK
MCLK
ns (max)
t
% (max)
(Limits)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
% (min)
SampCLK
Units
(min)
(min)
(min)
(min)
(min)