stlc3040 STMicroelectronics, stlc3040 Datasheet - Page 18

• Manufacturer Part Number: stlc3040
• Description: Subscriber Line Interface Codec Filter, Cofislic
• Manufacturer: STMicroelectronics

STLC3040
CK_FAIL Receiving Clock and/or Synchronization
signals failures
Bits ILIM, TEMP, VB_2 have 7ms persistance
fixed.
4.7.1.2 COP Command
Every COP command is started by the Start Ad-
dress. A second byte contains the RAM address
related to the programmable filters.
Address is defined by the least significative five
bits except the third one which identifies a COP
command.
COP commands consist of maximum 14 bytes
used to set and monitor digital filter coefficients.
COP register:
COD2 = 0 Identifies a COP command COD5,
COD4, COD3, COD1, COD0 bits identify filters
address as shown here below (Table 10).
For every coefficient, but B filter, with 14bit width
the Least significant Byte is sent first. In the Most
Significant Byte the first two bits must be stuffed
with 0.
For B Filter the 14 bytes are the result of the con-
catenation of the 8 coefficients of 14 bits
4.7.1.3 SOP Command
Reading and writing of CR and SOP register is
performed via SOP commands. Configuration,
operation and test data can be set and updated
by this command. As for every Monitor channel
Table 10:
Filters coefficients must be evaluated using a proper ST simulation software.
18/49
BIT7
= 1 Temperature Alarm from HV (L3000N,
= 0 no Detected Clock or Sync fails
= 1 Detected Clock or Sync fails
X
R/W = 0 Subsequent bytes are written to
COD5
L3000S, STLC3170)
0
0
0
0
1
0
1
BIT6
R/W COD5 COD4 COD3 COD2 COD1 COD0
= 1 Subsequent bytes are read from
COFISLIC
COFISLIC
BIT5 BIT4
COD4
0
0
0
1
0
1
0
BIT3 BIT2
COD3
0
0
1
1
0
1
0
BIT1
COD1
0
1
0
1
0
0
1
BIT0
command the SOP is started by Start Byte, in
downstream, followed by a byte that sets the SOP
register.
SOP register:
R/W = 0 Write to Cofislic
POL = 0 Normal Polarity Feeding
RST = 0 Normal Operation
After a reset, RST is set to 1. RST is toggled to 0
after a SOP read operation with LSEL bits pro-
grammed to 00b.
COD0
BIT7
If R/W = 0
If R/W = 1
SOP *: during the on going SOP command SOP* is
LSEL1
LSEL1
1
1
1
1
1
1
1
X
0
0
1
1
0
0
1
1
= 1 Reset, set the COFISLIC to the basic
= 1 Read Operation
= 1 Reverse Polarity Feeding
BIT6
R/W
the previously processed SOP command.
setting mode
LSEL0
LSEL0
Filter KA, KD
BIT5
POL
0
1
0
1
0
1
0
1
ADDRESS
Filter GR
Filter GX
Filter R
Filter B
Filter X
Filter Z
BIT4 BIT3
RST
Write to COFISLIC
No byte is following
Two bytes, which write CR1 and
CR2 Registers, follow
12 bytes, which set CR1,.,CR12
registers, follow
Not available
Read from COFISLIC
Replies the SOP * command
received by COFISLIC
Replies the SOP * command
received by COFISLIC, followed
by two bytes: CR1, CR2
Registers
Replies the SOP * command
received by COFISLIC, followed
by twelve bytes: CR1, CR2
CR12 Registers
Not available
0
Following Bytes
BIT2 BIT1
1
LSEL1 LSEL0
14
8
8
1
1
2
6
BIT0