stlc3040 STMicroelectronics, stlc3040 Datasheet - Page 22

• Manufacturer Part Number: stlc3040
• Description: Subscriber Line Interface Codec Filter, Cofislic
• Manufacturer: STMicroelectronics

STLC3040
RNGF2-RNGF0 select Ring frequency value
Ring Reset Value is 25 Hz
RNGV3-RNGV0 fix Ring Voltage programmation
step.
CR10 sets Teletax Voltage Level.
Reset Value: FF h
TTXV7-TTXV0
Teletax Amplitude [V] = TTXV (7:0) 10V
A dc drop (TTXV [7:3] 15mV 40)is applied as
indicated in electric specification section.
CR11 Bit (7:4) set External-indication threshold
R
ETHR [3:0] set the External-indication threshold:
for ETHR[3:0] = 0h, threshold = 0V;
for ETHR[3:0] > 0h:
Threshold = 8V + ETHR [3 : 0] 1V
TXONE and STRES3 must be always pro-
grammed to 0
DHPRX = 1 disable the Rx high pass filter
CR12 can mask the effect on SLCX of the six most
significant bits of Signalling Register. If a bit is
masked it will not affect the SLCX bit of upstream
C/I channel. The unmasked SR bits are used to
trigger an event-detect circuit and will latch the SR
signals into a shadow register whenever an event
occurs. An event is defined as a toggling of one or
more of the enabled SR bits. Once the interrupt is
set and the shadow registers are latched, any fur-
ther event does not influence the interrupt or the
shadow registers.
With the SR TOP READ command, the byte repre-
senting the SR will be sent out to the DU depend-
ing on the values of the MASK bits. For unmasked
SR bit its shadow register bit is sent out; otherwise
the value of SR bit is sent out. At the end of the
readout of the above byte, the interrupt bit is
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ETHR3 ETHR2 ETHR1 ETHR0 STRES3 TXONE DHPRX
TTXV7 TTXV6 TTXV5 TTXV4 TTXV3 TTXV2 TTXV1 TTXV0
BIT7 BIT6 BIT5 BIT4
BIT7
ESET
= 0h
= 1h
= 2h
= 3h
= 4h
= 5h
= 6h
= 7h
value = 10 h
BIT6
16.6Hz Ringing Frequency
20Hz Ringing Frequency
25Hz Ringing Frequency
50Hz Ringing Frequency
60Hz Ringing Frequency
Ringing Frequency not used
Ringing Frequency not used
Ringing Frequency not used
BIT5 BIT4
BIT3 BIT2
BIT3
BIT2 BIT1 BIT0
BIT1
rms
/255.
BIT0
X
cleared and two things could happen. If the con-
tents of the shadow register differ from the en-
abled SR (meaning there was at least one toggle
of the enabled SR bits between the time when the
interrupt bit is set and the TOP READ command),
then the SR byte will be latched into the shadow
register while the interrupt bit (SLCX) will remain
cleared (low) for 2 frames and then will be set
high. On the other hand, if the contents of the
shadow-register are equal to the enabled SR,
then the interrupt bit remains cleared and will be
set only by the next event. At reset, the shadow
register content mirrors that of SR register. A
mask-bit change causes SR to be latched in the
shadow-Register, nevertheless the SCLX bit is
cleared
Reset Value: FFh
HOOK Mask bit for Hook information in the sig-
nalling register
GNDK Mask bit for Ground Key information in the
signalling register
VB_2M Mask bit for half-battery information in the
signalling register
ILIM Mask bit for current limit information in the
signalling register
TEMP Mask bit for temperature information in the
signalling register
CLKF Mask bit for clock-fail information in the sig-
nalling register
COMRX = 0 Linear code in Rx is enabled
COMTX = 0 Linear code Tx is enabled
HOOK GNDK VB_2M ILIM
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2
= 1 No influence on SLCX bit (Upstream C/I.5)
= 0 Each change of the HOOK bit sets SLCX bit
= 1 No influence on SLCX bit (Upstream C/I.5)
= 0 Each change of the GNDK bit sets SLCX bit
= 1 No influence on SLCX bit (Upstream C/I.5)
= 0 Each change of the VB_2 bit sets SLCX bit
= 1 No influence on SLCX bit (Upstream C/I.5)
= 0 Each change of current limit bit sets
= 1 No influence on SLCX bit (Upstream C/I.5)
= 0 Each change of the temperature bit sets
= 1 No influence on SLCX bit (Upstream C/I.5)
= 0 Each change of the clock-fail bit sets SLCX
(Upstream C/I.5)
(Upstream C/I.5)
(Upstream C/I.5)
SLCX bit (Upstream C/I.5)
SLCX bit (Upstream C/I.5)
bit (Upstream C/I.5)
= 1 PCM in Tx is enabled
= 1 PCM in Rx is Enabled
TEMP CLKF COMRX COMTX
BIT1
BIT0