cs5566 Cirrus Logic, Inc., cs5566 Datasheet - Page 14

• Manufacturer Part Number: cs5566
• Description: ?2.5 V / 5 V, 5 Ksps, 24-bit ?? Adc
• Manufacturer: Cirrus Logic, Inc.

3/25/08
CS5566
3.1 Converter Operation
The converter should be reset after the power supplies and voltage reference are stable.
The CS5566 converts at 5 kSps when synchronously operated (CONV = VLR) from a 8.0 MHz master
clock. Conversion is initiated by taking CONV low. A conversion lasts 1600 master clock cycles, but if
CONV is asynchronous to MCLK there may be an uncertainty of 0-4 MCLK cycles after CONV falls to
when a conversion actually begins. This may extend the throughput to 1604 MCLKs
When the conversion is completed, the output word is placed into the serial port and RDY goes low. To
convert continuously, CONV should be held low. In continuous conversion mode with CONV held low, a
conversion is performed in 1600 MCLK cycles. Alternately RDY can be tied to CONV and a conversion
will occur every 1602 MCLK cycles.
To perform only one conversion, CONV should return high at least 20 master clock cycles before RDY
falls.
Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are
emptied from the serial port or if the conversion data is not read and CS is held low, RDY will go high two
MCLK cycles before the end of conversion. RDY will fall at the end of the next conversion when new data
is put into the port register.
See
Section 3.11 Serial Port
for information about reading conversion data.
Conversion performance can be affected by several factors. These include the choice of clock source for
the chip, the timing of CONV, and the choice of the serial port mode.
The converter can be operated from an internal oscillator. This clock source has greater jitter than an ex-
ternal crystal-based clock. Jitter may not be an issue when measuring DC signals, or very-low-frequency
AC signals, but can become an issue for higher frequency AC signals. For maximum performance when
digitizing AC signals, a low-jitter MCLK should be used.
To maximize performance, the CONV pin should be held low in the continuous conversion state to per-
form multiple conversions, or CONV should occur synchronous to MCLK, falling when MCLK falls.
If the converter is operated at maximum throughput, the SSC serial port mode is less likely to cause in-
terference to measurements as the SCLK output is synchronized to the MCLK. Alternately, any interfer-
ence due to serial port clocking can also be minimized if data is read in the SEC serial port mode when a
conversion is not in progress.
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