cs5566 Cirrus Logic, Inc., cs5566 Datasheet - Page 6

• Manufacturer Part Number: cs5566
• Description: ?2.5 V / 5 V, 5 Ksps, 24-bit ?? Adc
• Manufacturer: Cirrus Logic, Inc.

SWITCHING CHARACTERISTICS
T
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.
6
Master Clock Frequency
Master Clock Duty Cycle
Reset
RST Low Time
RST rising to RDY falling
Conversion
CONV Pulse Width
BP/UP setup to CONV falling
CONV low to start of conversion
Perform Single Conversion (CONV high before RDY falling)
Conversion Time
Sleep Mode
A
= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
Converter
CONVERT
Status
10. RDY will fall when the device is fully operational when coming out of sleep mode.
8. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.
9. If CONV is held low continuously, conversions occur every 1600 MCLK cycles.
RDY
If RDY is tied to CONV, conversions will occur every 1602 MCLKs.
If CONV is operated asynchronously to MCLK, a conversion may take up to 1604 MCLKs.
RDY falls at the end of conversion.
SLEEP low to low-power state
SLEEP high to device active (Note 10)
Parameter
Start of Conversion to RDY falling
Figure 1. Converter Status (Not to scale)
1182 - 1186 MCLKs
IDLE
Internal Oscillator
Internal Oscillator
External Clock
External Clock
1600 - 1604 MCLKs
3/25/08
(Note 8)
(Note 9)
Symbol
t
t
XIN
t
t
t
t
t
t
t
f
wup
cpw
bus
buh
con
con
scn
scn
res
clk
354 + 64 MCLKs
CONVERT
Min
0.5
40
20
6
1
4
0
-
-
-
-
-
-
t
bus
3084
1182
3083
Typ
240
ACTIVE
50
7
8
SDO
-
-
-
-
-
-
1604
1186
Max
8.1
60
8
-
-
-
-
-
-
-
-
CS5566
IDLE
DS806PP1
MCLKs
MCLKs
MCLKs
MCLKs
MCLKs
MCLKs
MHz
MHz
Unit
µs
µs
ns
µs
%