adc0854 National Semiconductor Corporation, adc0854 Datasheet - Page 4

• Manufacturer Part Number: adc0854
• Description: Multiplexed Comparator With 8-bit Reference Divider
• Manufacturer: National Semiconductor Corporation

f
t
t
t
t
t
t
C
C
Symbol
CLK
D1
r
SET-UP
HOLD
pd1
1H
AC Characteristics
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when
operating the device beyond its specified operating conditions
Note 2 All voltages are measured with respect to ground
Note 3 Internal zener diodes (approx 7V) are connected from V
to V
device is powered from V
Max of 6 5V It is recommended that a resistor be used to limit the max current into V
Note 4 Typicals are at 25 C and represent most likely parametric norm
Note 5 Tested and guaranteed to National AOQL (Average Outgoing Quality Level)
Note 6 Guaranteed but not 100% production tested These limits are not used to calculate outgoing quality levels
Note 7 Total unadjusted error includes comparator offset DAC linearity and multiplexer error It is expressed in LSBs of the threshold DAC’s input code
Note 8 For V
voltages one diode drop below ground or one diode drop greater than the V
(5V) can cause this input diode to conduct especially at elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward
bias of either diode This means that as long as the analog V
achieve an absolute 0 V
and loading
Note 9 Leakage current is measured with the clock not switching
Note 10 A 40% to 60% clock duty cycle range ensures proper operation at all clock frequencies In the case that an available clock has a duty cycle outside of
these limits then 1 6 mS
Note 11 With CS low and programming complete D0 is updated on each falling CLK edge However each new output is based on the comparison completed 0 5
clock cycles prior (see Figure 5 )
Note 12 Error specs are not guaranteed at 400 kHz (see graph Comparator Error vs f
Note 13 See text section 1 2
Note 14 Human body model 100 pF discharged through a 1 5 kX resistor
Note 15 Because the reference ladder of the ADC0852 is internally connected to V
current is included in the ADC0852’s supply current specification
IN
OUT
CC
t
t
0H
pd0
via a conventional diode Since the zener voltage equals the A D’s breakdown voltage the diode ensures that V
IN
Clock Frequency
(Note 12)
Rising Edge of Clock
to ‘‘DO’’ Enabled
Comparator Response
Time (Note 13)
Clock Duty Cycle
(Note 10)
CS Falling Edge or
Data Input Valid to
CLK Rising Edge
Data Input Valid after
CLK Rising Edge
CLK Falling Edge to
Output Data Valid
(Note 11)
Rising Edge of CS to
Data Output Hi-Z
Capacitance of Logic
Input
Capacitance of Logic
Outputs
(
b
)
t
V
IN
DC
s
(
a
a
to 5 V
CLK Low
Parameter
) the output will be 0 Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input
Functionality is therefore guaranteed for V
DC
input voltage range will therefore require a minimum supply voltage of 4 950 V
s
60 mS and 1 6 mS
t
r
e
t
f
MIN
MAX
MIN
MAX
MAX
MIN
MAX
MAX
e
20 ns T
IN
s
C
Not Including
Addressing Time
C
C
C
(see TRI-STATE Test Circuits)
L
L
L
L
or V
CLK HIGH
A
e
e
e
e
a
e
REF
100 pF
100 pF
10 pF R
100 pF R
to GND and V
25 C
does not exceed the supply voltage by more than 50 mV the output code will be correct To
a
Conditions
s
operation even though the resultant voltage at V
CC
%
supply Be careful during testing at low V
L
4
L
e
CC
e
10k
to GND The zener at V
2k
a
CC
CLK
ladder resistance cannot be directly tested for the ADC0852 Ladder
)
(Note 4)
Typ
650
650
125
5
5
a
can operate as a shunt regulator and is connected
DC
over temperature variations initial tolerance
CC
(Note 5)
Tested
levels (4 5V) as high level analog inputs
Limit
CC
CC
500
10
40
60
will be below breakdown when the
may exceed the specified Absolute
2
(Note 6)
Design
Limit
a
1000
1000
400
250
250
500
90
1 ms
1 f
Units
kHz
kHz
pF
pF
ns
%
%
ns
ns
ns
ns
ns
CLK