adc1213s125hn/c1 NXP Semiconductors, adc1213s125hn/c1 Datasheet - Page 28
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adc1213s125hn/c1
Manufacturer Part Number
adc1213s125hn/c1
Description
Adc1213s Series Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Serial Jesd204a Interface
Manufacturer
NXP Semiconductors
Datasheet
1.ADC1213S125HNC1.pdf
(39 pages)
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NXP Semiconductors
Table 21.
Default values are highlighted.
Table 22.
Default values are highlighted.
Table 23.
Default values are highlighted.
ADC1213S_SER
Product data sheet
Bit
7 to 4 -
3
2 to 0 INTREF[2:0]
Register offset
Decimal
+31
...
0
...
−32
Bit
7 to 3
2 to 0
Symbol
INTREF_EN
Symbol
-
TESTPAT_1[2:0]
Register Vref (address 0008h)
Digital offset adjustment (address 0013h)
Register Test pattern 1 (address 0014h)
Access
-
R/W
R/W
Access
-
R/W
DIG_OFFSET[5:0]
011111
...
000000
...
100000
0000
Value
0
1
000
001
010
011
100
101
110
111
Value
00000
000
001
010
011
100
101
110
111
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 March 2011
Description
not used
enable internal programmable VREF mode:
programmable internal reference:
Description
not used
digital test pattern:
disable
enable
0 dB (FS = 2 V)
−1 dB (FS = 1.78 V)
−2 dB (FS = 1.59 V)
−3 dB (FS = 1.42 V)
−4 dB (FS = 1.26 V)
−5 dB (FS = 1.12 V)
−6 dB (FS = 1 V)
not used
off
mid-scale
− FS
+ FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern, to be written in register 0015h and 0016h
‘010101...’
‘101010...’
Single 12-bit ADC; serial JESD204A interface
ADC1213S series
+31 LSB
...
0
...
−32 LSB
© NXP B.V. 2011. All rights reserved.
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