adc1206s040 NXP Semiconductors, adc1206s040 Datasheet
adc1206s040
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adc1206s040 Summary of contents
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... Single 12 bits ADC MHz, 55 MHz or 70 MHz Rev. 02 — 12 August 2008 1. General description The ADC1206S040/055/070 are a family of BiCMOS 12-bit Analog-to-Digital Converters (ADC) optimized for a wide range of applications such as cellular infrastructures, professional telecommunications, imaging, and digital radio. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz ...
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... Rev. 02 — 12 August 2008 ADC1206S040/055/070 = V33 to V34 = 3 3.6 V; AGND CCO V = 1.9 V; I(IN)(p-p) I(INN)(p- CCA Min Typ Max 4.75 5 ...
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... CLOCK DRIVER LATCHES ANALOG - TO - DIGITAL CONVERTER OVERFLOW/UNDERFLOW LATCH AGND4 DGND1 DGND2 Rev. 02 — 12 August 2008 ADC1206S040/055/070 V V OTC CE CCD1 CCD2 ADC1206S040/055/070 CMOS OUTPUTS CMOS OUTPUT 17 34 OGND D11 MSB D10 D9 ...
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... V) 16 not connected Rev. 02 — 12 August 2008 ADC1206S040/055/070 33 V CCO ...
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... V) 42 analog input voltage 43 complementary analog input voltage 44 analog ground 1 Limiting values Parameter Conditions analog supply voltage digital supply voltage output supply voltage supply voltage difference V CCA V CCD V CCA Rev. 02 — 12 August 2008 ADC1206S040/055/070 Min Max [1] 0.3 +7.0 [1] 0.3 +7.0 [1] 0.3 +7.0 V 1.0 +1.0 CCD V 1.0 +4.0 CCO V 1 ...
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... MHz 4.43 MHz MHz MHz MHz MHz i Rev. 02 — 12 August 2008 ADC1206S040/055/070 Min 0.3 0 may have any value between 0.3 V and +7.0 V provided that Conditions in free air = V37 to V38 and V15 to V17 = 4. 5. amb 1.6 V ...
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... Table 8 and 0 2 Table 1.75 V ref CCA3 I(INN Rev. 02 — 12 August 2008 ADC1206S040/055/070 = V37 to V38 and V15 to V17 = 4. 5. amb 1.6 V; typical values measured at V Min Typ Max 3. 0.8 3.83 - 4.12 2 CCD ...
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... MHz 400 kHz CCD = 3 amb CCA CCD = 3 amb Rev. 02 — 12 August 2008 ADC1206S040/055/070 = V37 to V38 and V15 to V17 = 4. 5. amb 1.6 V; typical values measured at V Min Typ Max - V 1.75 - CCA3 - 0 1 ...
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... 1 I(IN)(p-p) I(INN)(p-p) ref and and C CCO amb Symbol Parameter Conditions [4] Bandwidth ( MHz) clk B bandwidth 3 dB; full-scale input Harmonics second ADC1206S040H harmonic level f = 4.43 MHz MHz MHz MHz i ADC1206S055H 4.43 MHz MHz MHz ...
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... V33 to V34 = 3 3.6 V; AGND and DGND shorted together; T CCO 1 I(IN)(p-p) I(INN)(p-p) ref and and C CCO amb Symbol Parameter Conditions [5] Total harmonic distortion THD total harmonic ADC1206S040H; (f distortion f = 4.43 MHz MHz MHz MHz i ADC1206S055H 4.43 MHz MHz ...
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... V33 to V34 = 3 3.6 V; AGND and DGND shorted together; T CCO 1 I(IN)(p-p) I(INN)(p-p) ref and and C CCO amb Symbol Parameter Conditions Spurious free dynamic range; see SFDR spurious free ADC1206S040H; (f dynamic range f = 4.43 MHz MHz MHz MHz i ADC1206S055H 4.43 MHz i f ...
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... CLKN input is at PECL level and sampling is taken on the rising edge of the clock input CCD Rev. 02 — 12 August 2008 ADC1206S040/055/070 = V37 to V38 and V15 to V17 = 4. 5. amb 1.6 V; typical values measured at V Min Typ Max 0.25 ...
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... Mode selection Sample-and-hold selection Sample-and-hold active inactive; tracking mode Rev. 02 — 12 August 2008 ADC1206S040/055/070 ; see Figure 3. d( 1.75 V CCA3 Binary outputs Twos complement D11 to D0 outputs D11 to D0 0000 0000 0000 10 0000 0000 00 0000 0000 0000 ...
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... N sample w(clk)L t w(clk)H CLK sample N sample d(s) DATA DATA DATA Timing diagram Rev. 02 — 12 August 2008 ADC1206S040/055/070 sample sample h(o) DATA DATA d(o) © NXP B.V. 2008. All rights reserved. HIGH 50 % LOW HIGH 50 % LOW 014aaa396 ...
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... CCD output data t dLZ HIGH output data LOW 10 % 3.3 k ADC1206S 070 frequency on pin CE = 100 kHz Timing diagram and test conditions of 3-state output delay time Rev. 02 — 12 August 2008 ADC1206S040/055/070 dHZ dZH HIGH 90 % LOW t dZL 50 % TEST V CCO t dLZ t dZL S1 ...
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... Fig 6. Total Harmonic Distortion (THD function 014aaa373 SNR (dBFS) (1) (2) 100 f (MHz) i (1) 40 MHz (2) 55 MHz (3) 70 MHz Fig 8. Signal-to-Noise ratio (S/ function of input Rev. 02 — 12 August 2008 ADC1206S040/055/070 (3) 68 (2) ( (MHz input frequency (sample device). ...
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... Fig 10. Two-tone MHz ADC1206S040_055_070_2 Product data sheet ADC1206S040/055/070 Single 12 bits ADC MHz, 55 MHz or 70 MHz MHz. clk 20.1 MHz MHz. i clk Rev. 02 — 12 August 2008 014aaa375 20 25 measured output range (MHz) ...
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... ADC1206S040_055_070_2 Product data sheet Single 12 bits ADC MHz, 55 MHz or 70 MHz 1024 0.6 0.2 0.2 0.6 0 1024 Rev. 02 — 12 August 2008 ADC1206S040/055/070 014aaa377 2048 3072 output code 014aaa378 2048 3072 output code © NXP B.V. 2008. All rights reserved. 4096 4096 ...
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... MHz MHz (2) 40 (1) ( 4.43 MHz MHz i Rev. 02 — 12 August 2008 ADC1206S040/055/070 014aaa379 20 Input amplitude (dBFS 1 I(IN)(p-p) I(INN)(p-p) 014aaa380 20 Input amplitude (dBFS 1 I(IN)(p-p) I(INN)(p-p) © NXP B.V. 2008. All rights reserved MHz clk MHz clk ...
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... Fig 15. ENOB, SFDR and S function MHz 4.43 MHz clk i ADC1206S040_055_070_2 Product data sheet Single 12 bits ADC MHz, 55 MHz or 70 MHz 11 bits ( 1.9 2.1 2.3 V (V) ref 014aaa381 ; Fig 16. ADC full-scale; V ref Rev. 02 — 12 August 2008 ADC1206S040/055/070 2 (V) 2.2 1.8 1.4 1 1.3 1.5 1.7 1.9 V I(IN)(p-p) function CCA ref 014aaa382 2.1 2 (V) ...
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... V 11 ref n.c. n.c. n. 100 nF CLKN ADC1206S 070 CLK 270 014aaa387 Fig 19. Application diagram for TTL single-ended Rev. 02 — 12 August 2008 ADC1206S040/055/070 100 nF mode 5 V 100 (LSB ...
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... C16 100 CCA V CC FL4 P1 C14 C7 100 nF 330 nF ICI OUT MC78MO5CDT C2 4.7 F GND ( 750 LGT679 Rev. 02 — 12 August 2008 ADC1206S040/055/070 D10 22 D11 OTC 18 DGND2 17 n. CCD2 15 n ...
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... TM3 C11 TP2 FL3 C13 C19 C16 C15 FL1 C17 C18 Rev. 02 — 12 August 2008 ADC1206S040/055/070 TM2 IC2 C12 FL2 B11 TM1 1 014aaa391 C8 014aaa392 © ...
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... NXP Semiconductors Fig 23. PCB layout (top layer). Fig 24. PCB layout (ground layer). ADC1206S040_055_070_2 Product data sheet ADC1206S040/055/070 Single 12 bits ADC MHz, 55 MHz or 70 MHz 014aaa393 014aaa394 Rev. 02 — 12 August 2008 © NXP B.V. 2008. All rights reserved ...
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... Single 12 bits ADC MHz, 55 MHz or 70 MHz Alternative parts Description Single 10 bits ADC Single 10 bits ADC V i – V ideal in in ----------------------------------------------- – 1 and Rev. 02 — 12 August 2008 ADC1206S040/055/070 014aaa395 Sampling frequency [1] 55 MHz [1] 70 MHz © NXP B.V. 2008. All rights reserved ...
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... M/N, where M is the number of cycles and N is number SFDR noise P signal = 10 log ----------------------------------------- - P + noise distortion SINAD dB – Rev. 02 — 12 August 2008 ADC1206S040/055/070 V in DNL i = -------------------------------------------- - measured output range . t is the power of the terms which include the – – conforming ...
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... P signal = S log ---------------- - P noise and f t Rev. 02 — 12 August 2008 ADC1206S040/055/070 P harmonics log -------------------------- - P signal 1 SFDR log ----------------- - max s IMD3 20 25 measured output range (HHz) 2, these frequencies being chosen according to t 014aaa384 30 © NXP B.V. 2008. All rights reserved. ...
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... P signal – f – intermod Rev. 02 — 12 August 2008 ADC1206S040/055/070 – – © NXP B.V. 2008. All rights reserved ...
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... 2.5 scale (1) ( 0.4 0.25 10.1 10.1 12.9 0.8 0.2 0.14 9.9 9.9 12.3 REFERENCES JEDEC JEITA Rev. 02 — 12 August 2008 ADC1206S040/055/070 detail 12.9 0.95 1.3 0.15 0.15 0.1 12.3 0.55 EUROPEAN PROJECTION SOT307 (1) ( ...
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... Data sheet status Product data sheet • Corrections made to DNL value in • Corrections made to several entries in • Corrections made to note in Figure Product data sheet Rev. 02 — 12 August 2008 ADC1206S040/055/070 Change notice Supersedes - ADC1206S040_055_070_1 Table 1. Table © NXP B.V. 2008. All rights reserved ...
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... Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 12 August 2008 ADC1206S040/055/070 © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 12 August 2008 Document identifier: ADC1206S040_055_070_2 ...