adc1204006 National Semiconductor Corporation, adc1204006 Datasheet - Page 15

• Manufacturer Part Number: adc1204006
• Description: 12-bit, 40 Msps, 340 Mw A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

Applications Information
3.0 DATA OUTPUTS
The ADC12040 has 12 TTL/CMOS compatible Data Output
pins and the output format is offset binary. Valid offset binary
data is present at these outputs while the OE and PD pins
are low. While the t
timing, a simple way to capture a valid output is to latch the
data on the edge of the conversion clock (pin 10). Which
edge to use will depend upon the clock frequency and duty
cycle. If the rising edge is used, the t
determine maximum hold time acceptable of the driven de-
vice data inputs. If the falling edge of the clock is used, care
must be taken to be sure that adequate setup and hold times
are allowed for capturing the ADC output data.
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
spikes can cause on-chip noise that can couple into the
DR
and DR GND. These large charging current
OD
time provides information about output
FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer
OD
FIGURE 5. Differential Drive Circuit of Figure 4
time can be used to
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15
analog circuitry, degrading dynamic performance. Adequate
power supply bypassing and careful attention to the ground
plane will reduce this problem. Additionally, bus capacitance
beyond the specified 20 pF/pin will cause t
making it difficult to properly latch the ADC output data. The
result could be an apparent reduction in dynamic perfor-
mance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connect-
ing buffers (74AC541, for example) between the ADC out-
puts and any other circuitry. Only one driven input should be
connected to each output pin. Additionally, inserting series
100Ω resistors at the digital outputs, close to the ADC pins,
will isolate the outputs from trace and other circuit capaci-
tances and limit the output currents, which could otherwise
result in performance degradation. See Figure 4.
While the ADC12040 will operate with V
1.8V, t
timing when using reduced V
OD
increases with reduced V
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DR
.
DR
. Be careful of external
DR
voltages down to
OD
to increase,
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