adc12d1000/1600ciut/nopb National Semiconductor Corporation, adc12d1000/1600ciut/nopb Datasheet
adc12d1000/1600ciut/nopb
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adc12d1000/1600ciut/nopb Summary of contents
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... Data Acquisition Systems ■ RADAR/LIDAR ■ Set-top Box ■ Consumer RF ■ Software Defined Radio 5.0 Block Diagram © 2010 National Semiconductor Corporation ADC12D1000/ADC12D1600 3.0 Features ■ Configurable to either 2.0/3.2 GSPS interleaved or 1.0/1.6 GSPS dual ADC ■ Pin-compatible with ADC10D1000/1500 and ADC12D1800 ■ Internally terminated, buffered, differential analog inputs ■ ...
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... Wideband Performance 7.0 Ordering Information Industrial Temperature Range (-40°C < T ADC12D1000/1600CIUT/NOPB ADC12D1000/1600CIUT ADC12D1600RB If Military/Aerospace specified devices are required, please contract the National Semiconductor Sales Office/Distributors for availability and specifications. IBIS models are available at: http://www.national.com/analog/adc/ibis_models. www.national.com Wideband Performance < +85°C) NS Package A Lead-free 292-Ball BGA Thermally Enhanced Package ...
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Connection Diagram FIGURE 1. ADC12D1000/1600 Connection Diagram The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance. See Section 18.5 SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS for more information. 3 ...
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General Description ......................................................................................................................... 1 2.0 Applications .................................................................................................................................... 1 3.0 Features ........................................................................................................................................ 1 4.0 Key Specifications ........................................................................................................................... 1 5.0 Block Diagram ................................................................................................................................ 1 6.0 Wideband Performance .................................................................................................................... 2 7.0 Ordering Information ....................................................................................................................... 2 8.0 Connection Diagram ........................................................................................................................ 3 9.0 Ball ...
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Out-Of-Range Indication .............................................................................................. 52 18.1.5 Maximum Input Range ................................................................................................ 52 18.1.6 AC-coupled Input Signals ............................................................................................ 52 18.1.7 DC-coupled Input Signals ............................................................................................ 52 18.1.8 Single-Ended Input Signals .......................................................................................... 52 18.2 THE CLOCK INPUTS ........................................................................................................... 53 18.2.1 CLK Coupling ............................................................................................................. 53 ...
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TABLE 3. Power and Ground Balls .............................................................................................................. 13 TABLE 4. High-Speed Digital Outputs .......................................................................................................... 14 TABLE 5. Package Thermal Resistance ........................................................................................................ 16 TABLE 6. Static Converter Characteristics ..................................................................................................... 17 TABLE 7. Dynamic Converter Characteristics TABLE 8. Analog Input/Output and Reference ...
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Ball Descriptions and Equivalent Circuits Ball No. Name H1/J1 VinI+/- N1/M1 VinQ+/- U2/V1 CLK+/- V2/W1 DCLK_RST+/- TABLE 1. Analog Front-End and Clock Balls Equivalent Circuit 7 Description Differential signal I- and Q-inputs. In the Non-Du- al Edge Sampling (Non-DES) ...
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Ball No. Name V C2 CMO C3/D3 Rext+/- C1/D2 Rtrim+/- E2/F3 Tdiode+/- www.national.com Equivalent Circuit Description Common Mode Voltage Output or Signal Coupling Select. If AC-coupled operation at the analog inputs is desired, this pin should be ...
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Ball No. Name Y4/W5 RCLK+/- Y5/U6 RCOut1+/- V6/V7 RCOut2+/- Equivalent Circuit Description Reference Clock Input. When the AutoSync feature is active, and the ADC12D1000/1600 is in Slave Mode, the internal divided clocks are synchronized with respect to this input clock. ...
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Ball No. Name V5 DES V4 CalDly D6 CAL B5 CalRun www.national.com TABLE 2. Control and Status Balls Equivalent Circuit Description Dual Edge Sampling (DES) Mode select. In the Non-Extended Control Mode (Non-ECM), when this input is set to logic-high, ...
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Ball No. Name U3 PDI V3 PDQ A4 TPM A5 NDM Y3 FSR W4 DDRPh Equivalent Circuit Description Power Down I- and Q-channel. Setting either input to logic-high powers down the respective I- or Q-channel. Setting either input to logic-low ...
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Ball No. Name B3 ECE C4 SCS C5 SCLK B4 SDI A3 SDO D1, D7, E3, F4, DNC W3 www.national.com Equivalent Circuit Description Extended Control Enable bar. Extended feature control through the SPI interface is enabled when ...
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Ball No. Name A2, A6, B6, C6, D8, D9, E1, F1, V H4, N4, R1, T1, A U8, U9, W6, Y2, Y6 G1, G3, G4, H2, J3, K3, L3, M3 N2, P1, P3, P4, R3, R4 A11, A15, ...
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Ball No. Name K19/K20 DCLKI+/- L19/L20 DCLKQ+/- K17/K18 ORI+/- L17/L18 ORQ+/- www.national.com TABLE 4. High-Speed Digital Outputs Equivalent Circuit Description Data Clock Output for the I- and Q-channel data bus. These differential clock outputs are used to latch the output ...
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Ball No. Name J18/J19 DI11+/- H19/H20 DI10+/- H17/H18 DI9+/- G19/G20 DI8+/- G17/G18 DI7+/- F18/F19 DI6+/- E19/E20 DI5+/- D19/D20 DI4+/- D18/E18 DI3+/- C19/C20 DI2+/- B19/B20 DI1+/- B18/C17 DI0+/- · · M18/M19 DQ11+/- N19/N20 DQ10+/- N17/N18 DQ9+/- P19/P20 DQ8+/- P17/P18 DQ7+/- R18/R19 ...
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Absolute Maximum Ratings (Note 1, Note 2) Supply Voltage ( Supply Difference max(V )- A/TC/DR/E min(V ) A/TC/DR/E Voltage on Any Input Pin (except V +/-) IN V ...
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Converter Electrical Characteristics Unless otherwise specified, the following apply after calibration for V unused channel terminated to AC ground, FSR Pin = High 1.0/1.6 GHz at 0.5 V with 50% duty cycle (as specified); V CLK ...
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Symbol Parameter (Note 12, Note 14) Non-DES Mode ENOB Effective Number of Bits SINAD Signal-to-Noise Plus Distortion Ratio SNR Signal-to-Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free Dynamic Range www.national.com ...
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Symbol Parameter (Note 12, Note 13, Note 14) DES Mode ENOB Effective Number of Bits SINAD Signal-to-Noise Plus Distortion Ratio SNR Signal-to-Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free Dynamic ...
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TABLE 8. Analog Input/Output and Reference Characteristics Symbol Parameter Analog Inputs V Analog Differential Input Full Scale IN_FSR Range C Analog Input Capacitance, IN Non-DES Mode (Note Analog Input Capacitance, DES Mode (Note 10) R Differential Input Resistance IN Common ...
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TABLE 9. I-Channel to Q-Channel Characteristics Symbol Parameter Offset Match Positive Full-Scale Match Negative Full-Scale Match Phase Matching (I, Q) X-TALK Crosstalk from I-channel (Aggressor) to Q-channel (Victim) Crosstalk from Q-channel (Aggressor) to I-channel (Victim) TABLE 10. Sampling Clock Characteristics ...
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TABLE 12. Digital Control and Output Pin Characteristics Symbol Parameter Digital Control Pins (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS) V Logic High Input Voltage IH V Logic Low Input Voltage IL I Input ...
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TABLE 13. Power Supply Characteristics Symbol Parameter I Analog Supply Current A I Track-and-Hold and Clock Supply TC Current I Output Driver Supply Current DR I Digital Encoder Supply Current E I Total Supply Current TOTAL P Power Consumption C ...
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Symbol Parameter t Pulse Width DCLK_RST± PWR t DCLK Synchronization Delay SYNC_DLY t Differential Low-to-High Transition LHT Time t Differential High-to-Low Transition HLT Time t Data-to-DCLK Setup Time SU t DCLK-to-Data Hold Time H t DCLK-to-Data Output Skew OSK Data ...
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Symbol Parameter t SCS-to-Serial Clock Falling Hold HCS Time t Bus turn-around time BSU TABLE 16. Calibration Symbol Parameter t Calibration Cycle Time CAL t CAL Pin Low Time CAL_L t CAL Pin High Time CAL_H t Calibration delay determined ...
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Note 14: The Fs/2 spur was removed from all the dynamic performance spectifications. Note 15: Proper common mode voltage must be maintained to ensure proper output codes, especially during input overdrive. Note 16: The NPR was measured using an Agilent ...
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Specification Definitions APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the CLK input, after which the signal present at the input pin is sampled inside the device the variation in aperture ...
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SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the differ- ence, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that ...
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Transfer Characteristic FIGURE 3. Input / Output Transfer Characteristic 29 30091622 www.national.com ...
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Timing Diagrams www.national.com FIGURE 4. Clocking in 1:2 Demux Non-DES Mode* FIGURE 5. Clocking in Non-Demux Non-DES Mode* 30 30091659 30091660 ...
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FIGURE 7. Clocking in Non-Demux Mode DES Mode* * The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the ...
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FIGURE 9. Power-on and On-Command Calibration Timing www.national.com FIGURE 8. Data Clock Reset Timing (Demux Mode) FIGURE 10. Serial Interface Timing 32 30091620 30091625 30091619 ...
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Typical Performance Plots 1.9V 1.0/1.6 GHz CLK DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25MHz ...
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DNL vs. TEMPERATURE (ADC12D1000) 0.50 0.25 0.00 -0.25 -0.50 -50 0 TEMPERATURE (°C) ENOB vs. TEMPERATURE (ADC12D1000 NON-DES MODE DES MODE 6 -50 0 TEMPERATURE (°C) ENOB vs. SUPPLY VOLTAGE (ADC12D1000 NON-DES ...
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ENOB vs. CLOCK FREQUENCY (ADC12D1000 NON-DES MODE DES MODE 6 0 250 500 750 CLOCK FREQUENCY (MHz) ENOB vs. INPUT FREQUENCY (ADC12D1000 NON-DES MODE DES MODE 6 0 500 1,000 INPUT FREQUENCY ...
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SNR vs. TEMPERATURE (ADC12D1000 NON-DES MODE DES MODE 52 -50 0 TEMPERATURE (°C) SNR vs. SUPPLY VOLTAGE (ADC12D1000 NON-DES MODE DES MODE 52 1.6 1 (V) SNR vs. ...
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SNR vs. INPUT FREQUENCY (ADC12D1000 NON-DES MODE DES MODE 52 0 500 1,000 INPUT FREQUENCY (MHz) THD vs. TEMPERATURE (ADC12D1000) -40 -50 -60 -70 NON-DES MODE DES MODE -80 - TEMPERATURE (°C) THD ...
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THD vs. CLOCK FREQUENCY (ADC12D1000) -40 -50 -60 -70 NON-DES MODE DES MODE -80 0 250 500 CLOCK FREQUENCY (MHz) THD vs. INPUT FREQUENCY (ADC12D1000) -40 -50 -60 -70 NON-DES MODE DES MODE -80 0 500 INPUT FREQUENCY (MHz) SFDR ...
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SFDR vs. SUPPLY VOLTAGE (ADC12D1000 NON-DES MODE DES MODE 40 1.6 1.8 2 (V) SFDR vs. CLOCK FREQUENCY (ADC12D1000 NON-DES MODE DES MODE 40 0 250 500 750 CLOCK FREQUENCY ...
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SPECTRAL RESPONSE AT FIN = 498 MHz (ADC12D1000) 0 NON-DES MODE -25 -50 -75 -100 0 100 200 300 FREQUENCY (MHz) SPECTRAL RESPONSE AT FIN = 498 MHz (ADC12D1000) 0 DES MODE -25 -50 -75 -100 0 250 500 FREQUENCY ...
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FULL POWER BANDWIDTH (ADC12D1000 -12 NONDES DES DESIQ -15 0 1,000 2,000 INPUT FREQUENCY (MHz) POWER CONSUMPTION vs. CLOCK FREQUENCY (ADC12D1000) 5.0 4.5 4.0 3.5 3.0 2.5 DEMUX NON-DEMUX 2.0 0 250 500 750 CLOCK FREQUENCY ...
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Functional Description The ADC12D1000/1600 is a versatile A/D converter with an innovative architecture which permits very high speed oper- ation. The controls available ease the application of the de- vice to circuit solutions. Optimum performance requires adherence to the ...
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This feature is pin-controlled only and remains active during both Non-ECM and ECM. See Section 17.3.2.5 Demux/Non- demux Mode for more information. 17.2.1.3 Dual Data Rate Phase Pin (DDRPh) The Dual Data Rate Phase (DDRPh) Pin selects whether the ADC12D1000/1600 ...
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Extended Control Mode In Extended Control Mode (ECM), most functions are con- trolled via the Serial Interface. In addition to this, several of the control pins remain active. See Table 20 is selected by setting the ECE Pin to ...
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FIGURE 12. Serial Data Protocol - Write Operation 45 30091693 www.national.com ...
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FEATURES The ADC12D1000/1600 offers many features to make the device convenient to use in a wide variety of applications. Feature Selected via V AC/DC-coupled Mode Selection Input Full-scale Range Selected via FSR Adjust Input Offset Adjust Setting DES/Non-DES Mode ...
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Input Control and Adjust There are several features and configurations for the input of the ADC12D1000/1600 so that it may be used in many dif- ferent applications. This section covers AC/DC-coupled Mode, input full-scale range adjust, input offset adjust, ...
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FIGURE 13. DDR DCLK-to-Data Phase Relationship 17.3.2.2 LVDS Output Differential Voltage The ADC12D1000/1600 is available with a selectable higher or lower LVDS output differential voltage. This parameter is V and may be found in Table 12. The desired voltage may ...
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DNL and INL, which results in the maximum dynamic performance, as measured by: SNR, THD, SINAD (SNDR) and ENOB. 17.3.3.1 Calibration Control Pins and Bits Table summary of the pins and bits used ...
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Read exactly 240 times the Calibration Values register (Addr: 5h). The register values are R0, R1, R2... R239. The contents of R<239:0> should be stored. 5. Power up I- and Q-channels to original setting. 6. Set SSC (Addr: 4h, ...
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Applications Information 18.1 THE ANALOG INPUTS The ADC12D1000/1600 will continuously convert any signal which is present at the analog inputs, as long as a CLK signal is also provided to the device. This section covers important aspects related to ...
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FSR and the Reference Voltage The full-scale analog differential input range (V ADC12D1000/1600 is derived from an internal bandgap ref- erence. In Non-ECM, this full-scale range has two settings controlled by the FSR Pin; see Section 17.2.1.9 Full-Scale Input ...
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The range of this termination resistor is specified 18.2 THE CLOCK INPUTS The ADC12D1000/1600 has a differential clock input, CLK+ and CLK-, which must be driven with an AC-coupled, differ- ential ...
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Output Data Rate The data is produced at the output at the same rate it is sam- pled at the input. The minimum recommended input clock rate for this device see Table CLK(MIN) ble to operate ...
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The DCLK_RST signal can be asserted asynchronously to the input clock. If DCLK_RST is asserted, the DCLK output is held in a designated state (logic-high) in Demux Mode; in Non-Demux Mode, the DCLK continues to function normally. Depending upon when ...
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FIGURE 19. Power and Grounding Example 56 30091602 ...
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Thermal Management The Heat Slug Ball Grid Array (HSBGA) package is a modified version of the industry standard plastic BGA (Ball Grid Array) package. Inside the package, a copper heat spreader cap is The center balls are connected to ...
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ADC and t CalDly tity. For the purpose of this section assumed that CalDly is set as recommended. The Control Bits or Pins must be set or written to configure the ADC12D1000/1600 in ...
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FIGURE 23. Power-on with Control Pins set by FPGA post Power-on Cal 18.6.2 Power-on and Data Clock (DCLK) Many applications use the DCLK output for a system clock. For the ADC12D1000/1600, each I- and Q-channel has its own DCLKI and ...
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Clocking Device The clock source can be a PLL/VCO device such as the LMX2531LQxxxx family of products. The specific device should be selected according to the desired ADC sampling clock frequency. The ADC12D1000/1600RB uses the LMX2531LQ1910E/1570E, with the ADC ...
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Register Definitions Ten read/write registers provide several control and configuration options in the Extended Control Mode. These registers have no effect when the device is in the Non-extended Control Mode. Each register description below also shows the Power-On Reset ...
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Configuration Register 1 Addr: 0h (0000b) Bit Name CAL DPS OVS TPM POR Bit 15 CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration is initiated. This bit ...
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Reserved Addr: 1h (0001b) Bit Name POR Bits 15:0 Reserved. Must be set as shown. I-channel Offset Adjust Addr: 2h (0010b) Bit Name Res OS POR 0 0 ...
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Calibration Adjust Addr: 4h (0100b) Bit Name Res CSS POR Bit 15 Reserved. Must be set as shown. Bit 14 CSS: Calibration Sequence Select. The default 1b selects the following calibration sequence: ...
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Reserved Addr: 8h (1000b Bit Name POR Bits 15:0 Reserved. Must be set as shown. Reserved Addr: 9h (1001b) Bit Name POR Bits 15:0 ...
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Aperture Delay Coarse Adjust Addr: Ch (1100b Bit Name POR Bits 15:4 CAM(11:0): Coarse Adjust Magnitude. This 12-bit value determines the amount of delay that will be applied to the input CLK ...
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AutoSync Addr: Eh (1110b) Bit Name DRC(8:0) POR Bits 15:7 DRC(8:0): Delay Reference Clock (8:0). These bits may be used to increase the delay on the input reference clock when synchronizing multiple ...
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Physical Dimensions NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-034, VARIATION BAL-2. www.national.com inches (millimeters) unless otherwise noted 292-Ball BGA Thermally Enhanced Package Order Number ADC12D1000/1600CUIT NS Package Number UFH292A 68 ...
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Notes 69 www.national.com ...
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