adc12dl080civs National Semiconductor Corporation, adc12dl080civs Datasheet

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adc12dl080civs

Manufacturer Part Number
adc12dl080civs
Description
Dual 12-bit, 80 Msps, A/d Converter For If Sampling
Manufacturer
National Semiconductor Corporation
Datasheet

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© 2006 National Semiconductor Corporation
ADC12DL080
Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling
General Description
The ADC12DL080 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 12-bit digital words at 80 Megasamples per
second (MSPS). This converter uses a differential, pipeline
architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize power consumption
while providing excellent dynamic performance and a 600
MHz Full Power Bandwidth. Operating on a single +3.3V
power supply, the ADC12DL080 achieves 11.0 effective bits
at Nyquist and consumes just 447mW at 80 MSPS. The
Power Down feature reduces power consumption to 50 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times V
ended input. Full use of the differential input is recom-
mended for optimum performance. Duty cycle stabilization
and output data format are selectable. The output data can
be set for offset binary or two’s complement.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC12DL080 can be con-
nected to a separate supply voltage in the range of 2.4V to
the analog supply voltage. This device is available in the
64-lead TQFP package and will operate over the industrial
temperature range of −40˚C to +85˚C. An evaluation board is
available to ease the evaluation process.
Connection Diagram
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
REF
with the possibility of a single-
DS201694
Features
n Single +3.3V supply operation
n Internal sample-and-hold
n Internal or External reference
n Outputs 2.4V to 3.6V compatible
n Power down mode
n Duty Cycle Stabilizer
n Pin compatible with ADC12DL040, ADC12DL065,
Key Specifications
n Resolution
n Max Conversion Rate
n DNL
n SNR (f
n SNR (f
n SFDR (f
n SFDR (f
n Power Consumption
Applications
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL, Cable Modems
ADC12DL066
— Operating
— Power Down Mode
IN
IN
IN
IN
=40MHz)
=200MHz)
=40MHz)
=200MHz)
20169401
±
February 2006
447 mW (typ)
www.national.com
0.4 LSB (typ)
50 mW (typ)
69 dB (typ)
67 dB (typ)
82 dB (typ)
81 dB (typ)
80 MSPS
12 Bits

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adc12dl080civs Summary of contents

Page 1

... TQFP package and will operate over the industrial temperature range of −40˚C to +85˚C. An evaluation board is available to ease the evaluation process. Connection Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation Features n Single +3.3V supply operation n Internal sample-and-hold n Internal or External reference n Outputs 2 ...

Page 2

... Ordering Information Industrial (−40˚C ≤ T ADC12DL080CIVS ADC12DL080EVAL Block Diagram www.national.com ≤ +85˚C) Package A 64 Pin TQFP Evaluation Board 2 20169402 ...

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Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I A− B− REF 11 REFSEL/DCS ...

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Pin Descriptions and Equivalent Circuits Pin No. Symbol 21 OF/DOEN 22 OEA/OF 41 OEB/DRDY 59 PD 24–29 DA0–DA5 34–39 DA6-DA11 42–47 DB0–DB5 52–57 DB6-DB11 www.national.com (Continued) Equivalent Circuit OF/DOEN selects the output format (OF) or enables the DRDY output (DOEN). ...

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Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG POWER 9, 18 10, 17, AGND 20, 61, 64 DIGITAL POWER 33 32, 49 DGND 30 23, 31, ...

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Absolute Maximum Ratings 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications – Voltage on Any Input or ...

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Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V +2.5V 0V, External V = +1.0V, f REF limits apply for all ...

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DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V +2.5V 0V, External V = +1.0V, f REF limits apply for ...

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AC Electrical Characteristics Note 3: When the input voltage at any pin exceeds the power supplies (that is maximum package input current rating limits the number of pins that can safely exceed the power supplies with an ...

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Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...

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Timing Diagram Transfer Characteristic Output Timing FIGURE 1. Transfer Characteristic 11 20169409 20169410 www.national.com ...

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Typical Performance Characteristics DNL, INL specifications apply for AGND = DGND = DR GND = 0V MHz pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for T CLK IN L ...

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Typical Performance Characteristics DNL, INL specifications apply for AGND = DGND = DR GND = 0V MHz pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for T CLK IN L ...

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Typical Performance Characteristics for AGND = DGND = DR GND = 0V MHz pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are L dBc. Boldface limits ...

Page 15

Typical Performance Characteristics for AGND = DGND = DR GND = 0V MHz pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are L dBc. Boldface limits ...

Page 16

Typical Performance Characteristics for AGND = DGND = DR GND = 0V MHz pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are L dBc. Boldface limits ...

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Typical Performance Characteristics for AGND = DGND = DR GND = 0V MHz pF/pin, Duty Cycle Stabilizer On. Units for SNR and SINAD are dBFS. Units for SFDR and Distortion are L dBc. Boldface limits ...

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Functional Description Operating on a single +3.3V supply, the ADC12DL080 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The user has the choice of ...

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Applications Information 20169412 FIGURE 3. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion For differential operation, each analog input pin of the differ- ential pair should have a peak-to-peak voltage equal to the ...

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Applications Information with a series RC to ground such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is where t is the signal propagation rate down the clock line, PD ...

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Applications Information FIGURE 4. Application Circuit using Transformer Drive Circuit FIGURE 5. Optional Amplifier Drive for Circuit in Figure 4 4.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 ...

Page 22

Applications Information exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DR GND pins should NOT be connected to system ground in close prox- imity to any of the ADC12DL080’s other ground ...

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Applications Information The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected be- tween the converter’s input pins and ground or to the ...

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... Deutsch Tel: +49 (0) 69 9508 6208 English www.national.com Français Tel: +33 ( 8790 64-Lead TQFP Package Ordering Number ADC12DL080CIVS NS Package Number VECO64A 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness ...

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