adc12l032 National Semiconductor Corporation, adc12l032 Datasheet - Page 6
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adc12l032
Manufacturer Part Number
adc12l032
Description
3.3v Self-calibrating 12-bit Plus Sign Serial I/o A/d Converters With Mux And Sample/hold
Manufacturer
National Semiconductor Corporation
Datasheet
1.ADC12L032.pdf
(35 pages)
www.national.com
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
V
V
I
I
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
V
V
I
+I
−I
POWER SUPPLY CHARACTERISTICS
I
I
I
f
f
t
Symbol
IN(1)
IN(0)
OUT
D
A
REF
Symbol
CK
SK
C
IN(1)
IN(0)
OUT(1)
OUT(0)
+
SC
SC
+
DC and Logic Electrical Characteristics
The following specifications apply for V
sion mode, f
1.250V common-mode voltage, and 10(t
T
AC Electrical Characteristics
The following specifications apply for V
sion mode, t
with fixed 1.250V common-mode voltage, and 10(t
T
MIN
A
= T
to T
J
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE Output Current
Output Short Circuit Source Current
Output Short Circuit Sink Current
Digital Supply Current
Positive Analog Supply Current
Reference Input Current
= T
Conversion Clock (CCLK) Frequency
Serial Data Clock SCLK Frequency
Conversion Clock Duty Cycle
Serial Data Clock Duty Cycle
Conversion Time
MAX
MIN
CK
r
; all other limits T
= t
= f
to T
f
= 3 ns, f
SK
MAX
= 5 MHz, R
Parameter
Parameter
; all other limits T
CK
= f
A
SK
= T
S
= 25Ω, source impedance for V
= 5 MHz, R
J
= 25˚C. (Notes 7, 8, 9)
+
+
CK
= V
= V
A
) acquisition time unless otherwise specified. Boldface limits apply for T
= T
A
A
+ = V
+ = V
S
V
V
V
V
V
V
V
V
V
V
V
Awake
CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off
Awake
CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off
Awake
CS = HIGH, Powered Down
J
+
+
IN
IN
+
+
+
OUT
OUT
OUT
OUT
= 25Ω, source impedance for V
= 25˚C. (Note 17)
= 3.6V
= 3.0V
= 3.0V, I
= 3.0V, I
= 3.0V, I
CK
= 3.3V
= 0V
D
D
12-Bit + Sign or 12-Bit
8-Bit + Sign or 8-Bit
+ = +3.3 V
+ = +3.3 V
= 0V
= 3.3V
= 0V
= V
) acquisition time unless otherwise specified. Boldface limits apply for
D
+
Conditions
OUT
OUT
OUT
Conditions
6
DC
= −360 µA
= − 10 µA
= 1.6 mA
DC
, V
, V
REF
REF
REF
+ and V
+ = +2.500 V
+ = +2.500 V
REF
(Note 10)
REF
Typical
44(t
21(t
− ≤ 25Ω, fully-differential input with fixed
10
10
+ and V
1
0
CK
CK
DC
DC
)
)
, V
, V
REF
REF
(Note 10)
REF
Typical
Limits (Note 11)
−0.005
0.005
−0.1
− = 0 V
600
− = 0 V
0.1
1.1
2.2
0.1
0.1
14
16
12
10
70
− ≤ 25Ω, fully-differential input
44(t
21(t
8.8
4.2
40
60
40
60
5
5
CK
CK
DC
DC
)
)
, 12-bit + sign conver-
, 12-bit + sign conver-
(Note 11)
Limits
−1.0
−3.0
2.0
0.8
1.0
2.4
2.9
0.4
3.0
6.5
8.0
1.5
3.0
Units (Limits)
MHz (max)
MHz (max)
MHz (min)
Hz (min)
µs (max)
µs (max)
% (max)
% (max)
% (min)
% (min)
A
(max)
(max)
mA (max)
mA (max)
= T
µA (max)
µA (max)
µA (max)
mA (min)
mA (min)
µA (min)
(Limits)
V (max)
V (max)
V (min)
V (min)
V (min)
Units
µA
µA
µA
µA
µA
µA
J
=