adc12l066civyx National Semiconductor Corporation, adc12l066civyx Datasheet
adc12l066civyx
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adc12l066civyx Summary of contents
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... An evaluation board is available to facilitate the evaluation process. Connection Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation Features n Single supply operation n Low power consumption n Power down mode ...
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... Ordering Information Industrial (−40˚C ≤ T ADC12L066CIVY ADC12L066CIVYX ADC12L066EVAL Block Diagram www.national.com ≤ +85˚C) Package A 32 Pin LQFP 32 Pin LQFP Tape and Reel Evaluation Board 2 20032802 ...
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Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I − REF DIGITAL I/O 10 CLK Equivalent Circuit ...
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Pin Descriptions and Equivalent Circuits Pin No. Symbol 14–19, D0–D11 22–27 ANALOG POWER AGND DIGITAL POWER DGND GND www.national.com (Continued) Equivalent Circuit ...
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Absolute Maximum Ratings 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications – Voltage on Any Pin Input ...
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Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V +2.5V 0V +1.0V REF = all other limits ...
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Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V +2.5V 0V +1.0V REF = all other limits ...
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Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V +2.5V 0V +1.0V REF = all other limits ...
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AC Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V +2.5V 0V +1.0V REF = all ...
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Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...
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Timing Diagram Transfer Characteristic Output Timing FIGURE 1. Transfer Characteristic 11 20032809 20032810 www.national.com ...
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Typical Performance Characteristics V = 1.0V, unless otherwise stated. REF DNL DNL vs. Clock Duty Cycle INL www.national.com 3.3V 200328E6 DNL vs. Temperature 20032892 200328E7 12 = 2.5V MHz, ...
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Typical Performance Characteristics V = 1.0V, unless otherwise stated. (Continued) REF INL vs. Clock Duty Cycle SNR vs SNR vs 3.3V 2.5V 20032895 20032897 200328B1 13 ...
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Typical Performance Characteristics V = 1.0V, unless otherwise stated. (Continued) REF SNR vs. Clock Duty Cycle SNR vs. Temperature THD vs www.national.com 3.3V 2.5V 200328B3 200328B5 200328B7 14 ...
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Typical Performance Characteristics V = 1.0V, unless otherwise stated. (Continued) REF THD vs. f CLK THD vs. V REF SINAD vs 3.3V THD vs. Clock Duty Cycle 200328B9 200328C2 200328C4 ...
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Typical Performance Characteristics V = 1.0V, unless otherwise stated. (Continued) REF SINAD vs. V SINAD vs. Clock Duty Cycle SINAD vs. Temperature www.national.com 3.3V 200328C6 200328C8 200328D1 16 = 2.5V ...
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Typical Performance Characteristics V = 1.0V, unless otherwise stated. (Continued) REF SFDR vs SFDR vs. f CLK SFDR vs. V REF 3.3V 200328D3 SFDR vs. Clock Duty Cycle 200328D5 200328D7 ...
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Typical Performance Characteristics V = 1.0V, unless otherwise stated. (Continued) REF Power Consumption vs. f Spectral Response @ 10 MHz Input @ Spectral Response 50 MHz Input www.national.com 3.3V CLK 200328D9 Spectral ...
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Typical Performance Characteristics V = 1.0V, unless otherwise stated. (Continued) REF Spectral Response @ 100 MHz Input Spectral Response @ 240 MHz Input 3.3V 2.5V Spectral Response 200328J1 200328E5 19 ...
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Functional Description Operating on a single +3.3V supply, the ADC12L066 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 12 bits. Each analog input signal should have a ...
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Applications Information FIGURE 2. Expected Input Signal Range For angular deviations degrees from these two signals being 180 out of phase with each other, the full scale error in LSB can be described as approximately 1.79 ...
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Applications Information 2.1 CLK The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the range of 1 MHz to 80 MHz with rise and fall times of ...
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Applications Information FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer FIGURE 5. Differential Drive Circuit of Figure 4 (Continued) 23 20032813 20032814 www.national.com ...
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Applications Information FIGURE 6. Driving the Signal Inputs with a Transformer 4.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor within a centimeter of each ...
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Applications Information weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. Generally, analog and digital lines should cross each other at ...
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Applications Information cause faulty or erratic operation not uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot that goes above the power supply or below ground. A resistor of about 50Ω ...
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Physical Dimensions inches (millimeters) unless otherwise noted National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and ...