adc12qs065civs National Semiconductor Corporation, adc12qs065civs Datasheet - Page 14

• Manufacturer Part Number: adc12qs065civs
• Description: Quad 12-bit 65 Msps A/d Converter With Lvds Serialized Outputs
• Manufacturer: National Semiconductor Corporation

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Applications Information
2.3 Internal Regulator
The ADC12QS065 has an internal 1.8V regulator. The
VREG pins (pins 32 and 48) should each be bypassed to
AGND with a 1.0 µF capacitor.
3.0 DIGITAL INPUTS
Digital TTL/CMOS compatible inputs consist of CLK, DEN,
PD, REFPD, and INTREF.
3.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 20 MHz to 65 MHz with rise and fall times of 2
ns or less. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚.
The CLK signal also drives an internal state machine. If the
CLK is interrupted, or its frequency too low, the charge on
internal capacitors can dissipate to the point where the ac-
curacy of the output data will degrade. This is what limits the
minimum sample rate.
The clock line should be terminated at its source in the
characteristic impedance of that line. Take care to maintain a
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on
setting characteristic impedance.
It is highly desirable that the the source driving the ADC CLK
pin only drive that pin. However, if that source is used to
drive other things, each driven pin should be a.c. terminated
with a series RC to ground, such that the resistor value is
equal to the characteristic impedance of the clock line and
the capacitor value is
where t
"L" is the line length and Z
of the clock line. This termination should be as close as
possible to the ADC clock pin but beyond it as seen from the
clock source. Typical t
FR-4 board material. The units of "L" and t
same (inches or centimeters).
3.2 DEN
When the DEN pin is high, the LVDS outputs are in the active
state. When low, the output pins are in a high impedance
state. The ADC12QS065 will continue to convert whether the
pin is high or low, but the output can not be read while the pin
is low.
PD
is the signal propagation rate down the clock line,
PD
is about 150 ps/inch (60 ps/cm) on
O
is the characteristic impedance
PD
(Continued)
should be the
14
3.3 PD
The PD pin, when high, holds the ADC12QS065 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 3 mW
with a 65MHz clock.. The output data pins are undefined and
the data in the pipeline is corrupted while in the power down
mode.
The Power Down Mode Exit Cycle time is determined by the
value of the components on the reference bypass pins 58,
59, 60, 21, 22 and 23 and is as listed in the Electrical Tables
with the recommended components on the VREFT, VREFB
and VCOM reference bypass pins. These capacitors loose
their charge in the Power Down mode and must be re-
charged by on-chip circuitry before conversions can be ac-
curate. Smaller capacitor values allow slightly faster recov-
ery from the power down mode, but can result in a reduction
in SNR, SINAD and ENOB performance.
3.4 REFPD
When high, the REFPD pin will power down the internal
reference. With REFPD high, user must drive VREFT12,
VREFT34 and VREFB12 & VREFB34 externally. With
REFPD low, VREFT12, VREFT34, VREFB12 and VREFB34
are driven internally.
3.5 INTREF
When INTREF is connected to V
choices are selectable through the V
INTREF is connected to DGND, an external reference must
be applied to V
4.0 OUTPUTS
The ADC12QS065 has four Low Voltage Differential Signal-
ing (LVDS) Data Output pairs. Valid data is present at these
outputs while the DEN pin is high and the PD pin is low. The
OUTCLK and FRAME pins aid in data capture.
LVDS signals provide a high level of immunity to common
mode noise. The differential data signals consist of two
400mVpp signals that are 180 degrees out of phase. They
should be terminated with a 100Ω resistor near the receiver.
REF
. Section 2.1 Reference Pins
D
, two internal reference
REF
pin (pin 24). When