adc101c027cimkx National Semiconductor Corporation, adc101c027cimkx Datasheet - Page 17

• Manufacturer Part Number: adc101c027cimkx
• Description: I2c-compatible, 12-bit Analog-to-digital Converter Adc With Alert Function
• Manufacturer: National Semiconductor Corporation

1.6.2 Conversion Result Register
Pointer Address 00h (Read Only)
Default Value: 0000h
1.6.3 Alert Status Register
Pointer Address 01h (Read/Write)
Default Value: 00h
Bits
15
14:12
11:2
1:0
Bits
7:2
1
0
Alert Flag
D15
D7
D7
Name
Alert Flag
Reserved
Conversion Result
Reserved
Name
Reserved
Over Range
Alert Flag
Under Range
Alert Flag
D14
D6
D6
Description
When the Alert Bit Enable is set in the Configuration Register, this bit will be high if either alert
flag is set in the Alert Status Register. Otherwise, this bit is a zero. This bit indicates that an alert
condition has occured. The I
data registers to determine the source of the alert.
Always reads zeros.
The Analog-to-Digital conversion result. The Conversion result data is a 10-bit data word in
straight binary format. The MSB is D11.
Always reads zeros.
Description
Always reads zeros. Zeros must be written to these bits.
Bit is set to 1 when the measured voltage exceeds the V
V
controller writes a one to this bit. (2) The measured voltage decreases below the programmed
V
Alert Hold bit is cleared in the Configuration register. If the Alert Hold bit is set, the only way to
clear an over range alert is to write a one to this bit.
Bit is set to 1 when the measured voltage falls below the V
V
controller writes a one to this bit. (2) The measured voltage increases above the programmed
V
cleared in the Configuration register. If the Alert Hold bit is set, the only way to clear an under
range alert is to write a one to this bit.
Reserved
HIGH
HIGH
LOW
LOW
Conversion Result[5:0]
D13
D5
D5
limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The
limit plus the programmed V
limit minus the programmed V
limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The
Reserved
D12
D4
D4
2
C controller will typically read the Alert Status register and other
17
HYST
D11
HYST
D3
D3
value. The alert will only self-clear if the Alert Hold bit is
value (See Figure 9) . The alert will only self-clear if the
Conversion Result[9:6]
D10
D2
D2
HIGH
LOW
limit stored in the programmable
limit stored in the programmable
Over Range
Alert
D9
D1
D1
Reserved
Under Range
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Alert
D0
D0
D8