adc10732 National Semiconductor Corporation, adc10732 Datasheet - Page 25

• Manufacturer Part Number: adc10732
• Description: 10-bit Plus Sign Serial I/o A/d Converters With Mux, Sample/hold And Reference
• Manufacturer: National Semiconductor Corporation

Applications Hints
voltage (V
changing from 011 1111 1110 to 011 1111 1111. In bipolar
signed operation this only adjusts the positive full scale error.
3.4.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
should be properly adjusted first. A plus input voltage which
equals this desired zero reference plus
selected plus input and the zero reference voltage at the
corresponding minus input should then be adjusted to just
obtain the 000 0000 0000 to 000 0000 0001 code transition.
The full-scale adjustment should be made [with the proper
minus input voltage applied] by forcing a voltage to the plus
input which is given by:
where V
V
range. Both V
(V
code change from 011 1111 1110 to 011 1111 1111. Note,
when using a pseudo-differential or differential multiplexer
mode where V
GND range, the individual values of V
matter, only the difference sets the analog input voltage
span. This completes the adjustment procedure.
3.5 The Input Sample and Hold
The ADC10731/2/4/8’s sample/hold capacitor is imple-
mented in the capacitor array. After the channel address is
loaded, the array is switched to sample the selected positive
analog input. The sampling period for the assigned positive
input is maintained for the duration of the acquisition time (t
4.5 clock cycles.
Note: Diodes are 1N914.
Note: The protection diodes should be able to withstand the output current of the op amp under current limit.
MIN
REF
equals the low end (the offset zero) of the analog
= V
MAX
REF
REF
equals the high end of the analog input range,
+
MAX
REF
− V
= V
+ and V
REF
and V
REF
−
+
) voltage is then adjusted to provide a
– V
MIN
REF
REF
are ground referred. The V
− are placed within the V
−
) for a digital output code
(Continued)
REF
1
⁄
2
FIGURE 17. Protecting the Analog Inputs
and V
LSB is applied to
REF
− do not
+
and
REF
A
)
25
This acquisition window of 4.5 clock cycles is available to
allow the voltage on the capacitor array to settle to the
positive analog input voltage. Any change in the analog
voltage on a selected positive input before or after the ac-
quisition window will not effect the A/D conversion result.
In the simplest case, the array’s acquisition time is deter-
mined by the R
stray input capacitance C
and stray (C
resistance the analog input can be modeled as an RC net-
work as shown in Figure 16. The values shown yield an
acquisition time of about 1.1 µs for 10-bit unipolar or 10-bit
plus sign accuracy with a zero-to-full-scale change in the
input voltage. External source resistance and capacitance
will lengthen the acquisition time and should be accounted
for. Slowing the clock will lengthen the acquisition time,
thereby allowing a larger external source resistance.
The signal-to-noise ratio of an ideal A/D is the ratio of the
RMS value of the full scale input signal amplitude to the
value of the total error amplitude (including noise) caused by
the transfer function of the ideal A/D. An ideal 10-bit plus sign
A/D converter with a total unadjusted error of 0 LSB would
have a signal-to-(noise + distortion) ratio of about 68 dB,
which can be derived from the equation:
S/(N + D) = 6.02(n) + 1.76
where S/(N + D) is in dB and n is the number of bits.
FIGURE 16. Analog Input Model
S2
) capacitance (48 pF). For a large source
ON
(3 kΩ) of the multiplexer switches, the
S1
(3.5 pF) and the total array (C
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)