ad1843jst Analog Devices, Inc., ad1843jst Datasheet - Page 30

• Manufacturer Part Number: ad1843jst
• Description: Serial-port 16-bit Soundcomm Codec
• Manufacturer: Analog Devices, Inc.

AD1843
LD2MM
LD2M4:0
RD2MM
RD2M4:0
res
LX1MM
LX1M4:0
RX1MM
RX1M4:0
Address 3
Address 4
RD2MM
LD2MM
LX1MM
RX1MM
Data 15
Data 15
Data 7
Data 7
Left DAC2 Mix Mute
Left DAC2 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to 2.0 V p-p DAC2
Right DAC2 Mix Mute
Right DAC2 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to 2.0 V p-p DAC2
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Left Auxiliary 1 Mix Mute
Left Auxiliary 1 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to 2.0 V p-p DAC1
Right Auxiliary 1 Mix Mute
Right Auxiliary 1 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to 2.0 V p-p DAC1
0 = Mix Enabled
1 = Mix Muted
output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
0 = Mix Enabled
1 = Mix Muted
output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; when the PDNO bit in Control Register
Address 0 is set to “1” (all conversions disabled); or when the DDMEN bit (DAC2 to DAC1 analog mix disabled),
the DA2EN bit (DAC2 powered down), or the ANAEN bit (analog channels powered down) in Control Register Ad-
dress 27 is reset to “0.”
0 = Mix Enabled
1 = Mix Muted
output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
0 = Mix Enabled
1 = Mix Muted
output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
Data 14
Data 14
Data 6
Data 6
res
res
res
res
Data 13
Data 13
Data 5
Data 5
res
res
res
res
Mix Control—DAC2 to Mixer
Mix Control—Auxiliary 1 to DAC1
Data 12
RD2M4
Data 12
LD2M4
LX1M4
RX1M4
Data 4
Data 4
–30–
Data 11
RD2M3
Data 11
LD2M3
LX1M3
RX1M3
Data 3
Data 3
Data 10
RD2M2
Data 10
LD2M2
LX1M2
RX1M2
Data 2
Data 2
RD2M1
LD2M1
LX1M1
RX1M1
Data 9
Data 1
Data 9
Data 1
LD2M0
RD2M0
LX1M0
RX1M0
Data 8
Data 0
Data 8
Data 0
REV. 0