ad1843jst Analog Devices, Inc., ad1843jst Datasheet - Page 32

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ad1843jst

Manufacturer Part Number
ad1843jst
Description
Serial-port 16-bit Soundcomm Codec
Manufacturer
Analog Devices, Inc.
Datasheet
AD1843
RX3MM
RX3M4:0
res
LMCMM
LMCM4:0
RMCMM
RMCM4:0
res
MNMM
Address 7
Address 8
LMCMM
RMCMM
ALLMM
Data 15
Data 15
MNMM
Data 7
Data 7
Right Auxiliary 3 Mix Mute
Right Auxiliary 3 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Left Microphone Mix Mute
Left Microphone Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to 2.0 V p-p
Right Microphone Mix Mute
Right Microphone Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to 2.0 V p-p
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Mono Input Mix Mute
0 = Mix Enabled
1 = Mix Muted
2.0 V p-p DAC1 output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; when the PDNO bit in Control Register
Address 0 is set to “1” (all conversions disabled); or when the AAMEN bit (analog input to analog mix disabled), or
the ANAEN bit (analog channels powered down) in Control Register Address 27 is reset to “0.”
0 = Mix Enabled
1 = Mix Muted
DAC1 output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
0 = Mix Enabled
1 = Mix Muted
DAC1 output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; when the PDNO bit in Control Register
Address 0 is set to “1” (all conversions disabled); or when the AAMEN bit (analog input to analog mix disabled), or
the ANAEN bit (analog channels powered down) in Control Register Address 27 is reset to “0.”
0 = Mix Enabled
1 = Mix Muted
Data 14
Data 14
MNOM
Data 6
Data 6
res
res
res
Mix/Miscellaneous Control—Mono In to Mixer and Miscellaneous Settings
Data 13
Data 13
HPOM
Data 5
Data 5
res
res
res
Mix Control—Mic to Mixer
LMCM4
RMCM4
Data 12
Data 12
MNM4
Data 4
Data 4
HPOS
–32–
LMCM3
RMCM3
Data 11
Data 11
SUMM
MNM3
Data 3
Data 3
LMCM2
RMCM2
Data 10
Data 10
MNM2
Data 2
Data 2
res
LMCM1
RMCM1
DAC2T
MNM1
Data 9
Data 1
Data 9
Data 1
LMCM0
RMCM0
DAC1T
MNM0
Data 8
Data 0
Data 8
Data 0
REV. 0

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