tda8761am NXP Semiconductors, tda8761am Datasheet - Page 9

• Manufacturer Part Number: tda8761am
• Description: 9-bit Analog-to-digital Converter For Digital Video
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
2. Analog input voltages producing code 0 up to and including code 511:
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
4. f
5.
6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
1998 Nov 03
Timing (f
t
t
t
C
3-state output delay times; see Fig.5
t
t
t
t
SYMBOL
ds
h
d
dZH
dZL
dHZ
dLZ
L
9-bit analog-to-digital converter
for digital video
must not be less than 0.5 ns.
a) V
b) V
of the converter reference resistor ladder (corresponding to output codes 0 and 511 respectively) are connected to
pins V
a) The current flowing into the resistor ladder is
b) Since R
No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
input (square wave signal) in order to sample the signal and obtain correct output data.
GER
i
= 10 MHz and f
the reference voltage BOTTOM (V
produces data outputs equal to code 511 at T
to cover code 0 to code 511, is
codes at a given input voltage depends mainly on the difference V
supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the
matching between each of them is then optimized.
----------------------------------------- -
R
osB
osT
OB
RB
clk
=
(voltage offset TOP) is the difference between V
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
+
sampling delay time
output hold time
output delay time
digital output load
enable HIGH
enable LOW
disable HIGH
disable LOW
--------------------------------------------------- -
= 30 MHz; C
and V
R
R
V
L
L
511
L
, R
+
RT
OB
–
R
V
clk
OT
V
i(p-p)
PARAMETER
via offset resistors R
and R
0
= 30 MHz; f
will be kept reasonably constant from device to device. Consequently variation of the output
–
L
V
= 15 pF); see Fig.4; note 11
OT
i(p-p)
have similar behaviour with respect to process and temperature variation, the ratio
100
i
= 8 MHz and f
V
I
RB
=
OB
R
) at T
and R
L
V
V
CCO
CCO
I
amb
L
clk
I
=
OT
L
CONDITIONS
amb
= 4.75 V
= 3.15 V
= 20 MHz.
= 25 C.
----------------------------------------- -
R
=
as shown in Fig.3.
OB
----------------------------------------- -
R
= 25 C.
OB
+
9
V
R
R
RT
RT
+
L
L
R
(reference voltage TOP) and the analog input which
+
–
L
R
V
+
OT
RB
R
OT
RT
V
and the full-scale input range at the converter,
4
RT
V
MIN.
–
RB
V
and its variation with temperature and
RB
=
3
10
12
5.5
12
19
12
TYP.
0. ˙ 852
13
15
15
8.5
15
24
15
Product specification
V
MAX.
RT
TDA8761A
–
V
RB
ns
ns
ns
ns
pF
ns
ns
ns
ns
UNIT