tda8757c NXP Semiconductors, tda8757c Datasheet - Page 16

• Manufacturer Part Number: tda8757c
• Description: Tda8757c Triple 8-bit Adc 205 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 10111
Preliminary data
where:
In the event that several combinations of R and I
of the damping factor (
The combination of R and I
the optimum PLL performance.
where C
values are: C
Pin COAST is used to disconnect the PLL phase frequency detector during the frame
flyback (vertical blanking) or the unavailability of the CKREF signal. This signal can
normally be derived from the VSYNC signal.
The COAST signal may be active either HIGH or LOW by setting bit ‘Vlevel’ in the
control register, through the serial interface (Vlevel = 0 when HIGH).
It is possible to control the phase of the ADC clock (CKADC), through the serial
interface, with the included digital phase-shift controller. The phase register (5 bits)
enables to shift the phase by steps of 11.25 deg.
The CKREF signal is resynchronized by the synchro-block on the CKADC clock. The
new reference is available on pin CKREFO. This synchronization may be done either
with the CKREF signal directly, or with the output of the divider in the PLL (see
Figure
The selection is done via the serial interface by setting bit ‘Ckrs’ in the phase register
(Ckrs = 1 when the CKREF signal is used). The polarity of the signal on pin CKREFO
is controlled through the serial interface by setting bit ‘Ckrp’ in register DEMUX
(positive polarity if Ckrp = 0). The width of this signal is fixed to 8 clock cycles.
The PLL also provides a CKDATA clock. This clock is synchronized on the data
outputs regardless of the mode.
It is possible to delay the CKDATA clock with a constant time (
the outputs) by setting bit ‘Ckdd’ to logic 1 in register DEMUX. Moreover, it is possible
to invert the CKDATA clock, referenced to the outputs, by setting bit ‘Ckdp’ in
register DEMUX.
The maximum capacitive load for each clock output is 10 pF.
•
•
•
=
DR
horizontal line frequency of the incoming signal. The setting of this parameter is
performed through the serial interface with bits Di0 to Di11. These bits are present
in the VCO-, divider- and phase registers.
f
K
Table
ref
0
R C
-------------- -
= the VCO gain, which depends on the pixel frequency ranges given in
= the frequency of the signal.
PLL
3).
2
Z
10.
= the divider ratio, which is the ratio between the pixel frequency and the
Z
and C
Z
---------------------------------------------- -
DR
= 68 nF and C
P
PLL
are the external capacitors of the PLL loop filter. The recommended
Rev. 01 — 14 August 2002
K
0
C
I
cp
Z
for each couple becomes necessary.
+
cp
C
P
whose damping factor is the closest to 1.5, generates
P
= 150 pF.
cp
give the same result, a calculating
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Triple 8-bit ADC 205 Msps
TDA8757C
ns, compared to
16 of 38
(2)