tda8712t NXP Semiconductors, tda8712t Datasheet - Page 8

• Manufacturer Part Number: tda8712t
• Description: 8-bit Digital-to-analog Converters
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Notes
1. D0 to D7 are connected to V
2. The analog output voltages (V
3. The 3 dB analog output bandwidth is determined by real time analysis of the output transient at a maximum input
4. The worst case characteristics are obtained at the transition from input code 0 to 255 and if an external load
5. The data set-up time (t
6. The definition of glitch energy and the measurement set-up are shown in Fig.6. The glitch energy is measured at the
June 1994
Switching characteristics (f
t
t
t
t
t
t
Output transients (glitches; f
E
SU;DAT
HD;DAT
PD
S1
S2
d
g
8-bit digital-to-analog converters
SYMBOL
between V
code transition (code 0 to 255).
impedance greater than 75
measured with an active probe between V
been applied. All input data is latched at the rising edge of the clock. The output voltage remains stable (independent
of input data variations) during the HIGH level of the clock (CLK = HIGH). During a LOW-to-HIGH transition of the
clock (CLK = LOW), the DAC operates in the transparent mode (input data will be directly transferred to their
corresponding analog output voltages; see Fig.5.
be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge of the clock and still be recognized. The data hold time (t
edge of the clock that the input data must be stable in order to be correctly registered. A negative hold time indicates
that the data may be released prior to the rising edge of the clock and still be recognized.
input transition between code 127 and 128 and on the falling edge of the clock.
CCA
data set-up time
data hold time
propagation delay time
settling time 1
settling time 2
input to 50% output delay time
glitch energy from code
and each of these outputs is typically 75 .
PARAMETER
SU;DAT
clk
clk
CCD
) is the minimum period preceding the rising edge of the clock that the input data must
= 50 MHz; notes 4 and 5; see Figs 3, 4 and 5)
OUT
is connected between V
= 50 MHz; note 6; see Fig.6)
and CLK is connected to DGND.
and V
OUT
OUT
) are negative with respect to V
and AGND. No further load impedance between V
10% to 90% full-scale
change to 1 LSB
10% to 90% full-scale
change to 1 LSB
transition 127 to 128
CONDITIONS
OUT
8
or V
OUT
HD;DAT
and V
2.0
0.3
CCA
) is the minimum period following the rising
MIN.
CCA
. The specified values have been
(see Table 1). The output resistance
TDA8712; TDF8712
1.1
6.5
3.0
TYP.
1.0
1.5
8.0
5.0
30
Product specification
MAX.
OUT
and AGND has
ns
ns
ns
ns
ns
ns
LSB ns
UNIT